Signal generation circuit

• US 5,184,310 A
• Filed: 03/30/1990
• Issued: 02/02/1993
• Est. Priority Date: 03/31/1989
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Takenouchi, Norio
• Primary Examiner(s): Black, Thomas G.
• Assistant Examiner(s): Cosimano, Edward R.
• Application Number:
  US07/501,857
• Time in Patent Office: 1,040 Days
• Field of Search: 318/696, 318/811, 363/41, 364/550, 364/150, 364/185
• US Class Current: 702/124
• CPC Class Codes: F25B 2600/021 Inverters therefor
• CPC Class Codes: F25B 49/025 Motor control arrangements
• CPC Class Codes: H02M 7/53873 with digital control
• CPC Class Codes: Y02B 30/70 Efficient control or regulation technologies, e.g. for control of refrigerant flow, motor or heating

Abstract

Pulse wave modulation waveform signals of three-phase alternating-current necessary for driving a compressor used in an air-conditioner incorporating an inverter circuit are, for example, generated by preliminarily storing the reference waveform data in a ROM, reading out sequentially, and executing specified data conversion instructions. In a signal generation circuit of the invention, a waveform generation circuit for execution of such data conversion is provided independently of a central processing unit (CPU), and after setting initial data from the CPU, the waveform data are directly read into the waveform generation circuit from the ROM by DMA transfer system to perform data conversion. That is, the CPU is not related with the data conversion, and therefore it is not necessary to create waveform data reading program and data conversion program.

Claims

1. A signal generation circuit comprising:

memory means for storing waveform data used to generate an output signal;

central processing means for storing initial data in at least one register for addressing the waveform data, aid central processing means and the register being operatively connected by a data bus;

address specifying means for specifying an address in said memory means for the waveform data on the basis of the initial data stored in the register; and

signal processing means for processing the waveform data at the specified address on the basis of the initial data stored in the register to produce the output signal;

said at least one register including,

a start/end register for storing one of a start address and an end address of the initial data,

a sample time setting register for storing the time interval for reading out the waveform data from the memory,

a control register for storing a type of waveform data, and

plural counter registers for counting and storing the number of times the waveform data is read from memory.

2. A signal generation circuit as claimed in claim 1, said central processing circuit comprising central processing memory means for storing an operational program for processing and outputting the initial data to the register.

4. A signal generation circuit as claimed in claim 1 or 3, wherein the waveform data is stored in the memory based on a frequency of the output signals to be generated, and the waveform data is selected according to the initial data stored in the register.

5. A signal generation circuit as claimed in claim 1 or 3, further comprising:

a direct-current power source for generating direct-current electric power; and

inverting means for converting the direct-current electric power from the direct-current power source into alternating-current electric power, in accordance with the output signal produced by the signal processing means.

3. A signal generation circuit comprising:

central processing means for processing an output signal according to an operation program;

at least one register connected to the central processing means through a data bus, for storing initial data as a reference for the output signal;

memory means for storing the operation program and waveform data necessary to generate the output signal;

address specifying means for specifying an address of the waveform data stored in the memory means according to the initial data stored in the register;

signal processing means for processing the waveform data at the specified address on the basis of the initial data stored in the register in order to provide the output signal; and

switching means for switching the data bus so that it electrically connects the central processing means and the memory means when an instruction from the operational program is to be read from the memory means into the central processing means, and so that the data bus electrically connects the signal processing means and the memory means when the waveform data is to be read from the memory means into the signal processing means.

6. A signal generation circuit as claimed in claim 3, wherein the switching means switches the data bus from electrically connecting the central processing circuit and the memory, to electrically connecting the signal processing means and the memory, in response to a bus switching signal from the central processing means.

7. A signal generation circuit as claimed in claim 6, wherein the central processing means detects a time interval for specifying the address of the waveform data by the address specifying means, and generates the bus switching signal in response to the time interval so that the waveform data and operational program can be stored in said memory means.

8. A compressor controlling device comprising:

signal generation means including,

first read only memory for storing an operational program,

second read only memory for storing waveform data corresponding to a plurality of motor rotation speeds,

central processing means for addressing the operational program stored in said first read only memory and for addressing waveform data stored in said second read only memory,

random access memory for receiving and outputting a rotational speed from an external controller, and

waveform generating means for processing the waveform data addressed by said CPU in accordance with the operational program to generate a compressor control signal;

photocoupling means for removing noise from a direct-current output;

converting means for converting the direct-current output to a rectangular wave equal to a three phase alternating current according to the compressor control signal and the rotational speed stored in random access memory; and

compressor coil means for receiving the three phase alternating current for controlling a rotation speed of the compressor.

9. The compressor controlling device of claim 8, said photocoupling means including a plurality of phototransistors and said connecting means including a power supply circuit for supplying the direct current output and a plurality of transistors for converting the direct current output into the three phase alternating current output.

10. A signal generation circuit comprising:

random access memory for storing a rotational speed of a motor set by an external controller;

read only memory for storing an operational program and waveform data;

central processing means for addressing the operational program stored in said read only memory;

waveform generating means for addressing and processing waveform data in accordance with the operational program to generate a compressor control signal used to control a motor such that its rotational speed matches the rotational speed stored in said random access memory; and

line changeover means for operatively connecting said random access memory and said read only memory to said central processing means when the operational program is to read from said read only memory and for operatively connecting said random access memory and said read only memory to said waveform generating means when waveform data is to be read from said read only memory.