Active matrix liquid crystal display apparatus and method of producing the same

• US 5,185,601 A
• Filed: 01/08/1991
• Issued: 02/09/1993
• Est. Priority Date: 01/11/1990
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Hotta, Sadayoshi, Takeda, Mamoru, Tamura, Tatsuhiko
• Primary Examiner(s): Brier, Jeffery A.
• Assistant Examiner(s): AU, AMELIA MEGAN
• Application Number:
  US07/638,537
• Time in Patent Office: 763 Days
• Field of Search: 350/333, 350/336, 357/23.7, 340/784 CL, 359/59, 428/1
• US Class Current: 349/39
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A liquid crystal display apparatus includes a transistor array substrate having formed thereon an array of pixel electrodes arranged in a matrix to form pixels, an array of switching thin film transistors arranged in a matrix for driving the pixels, respectively, gate bus lines arranged in rows for applying scanning signals to the switching thin film transistors, and source bus lines arranged in columns for applying display data signals to the switching thin film transistors. A counter substrate has formed thereon a common counter electrode confronting the pixel electrodes, and a liquid crystal layer is sandwiched between the transistor array substrate and the counter substrate. The transistor array substrate further has formed thereon a common electrode disposed below the pixel electrodes through an insulating layer for constituting auxiliary capacitors with the pixel electrodes. The common electrode is extended to cover an area above each source bus line or each gate bus line through another insulating layer so as to shield the pixel electrodes from the source or gate bus lines.

Claims

1. A liquid crystal display apparatus comprising:

a transistor array substrate having formed thereon an array of pixel electrodes arranged in a matrix to form pixels, an array of switching thin film transistors arranged in a matrix for driving the pixels, respectively, gate bus lines arranged in rows for applying scanning signals to the switching thin film transistors, and source bus lines arranged in columns for applying display data signals to the switching thin film transistors;

a counter substrate having formed thereon a common counter electrode confronting the pixel electrodes; and

a liquid crystal layer sandwiched between the transistor array substrate and the counter substrate,

wherein the transistor array substrate has formed thereon a common electrode disposed below the pixel electrodes through an insulating layer for constituting an auxiliary capacitor between said common electrode and each of the pixel electrodes through the insulating layer, the common electrode being extended to cover an area above each source bus line or each gate bus line through another insulating layer so as to shield the pixel electrodes from the source bus lines or gate bus lines.

2. An apparatus according to claim 1, wherein each of the common electrode and the pixel electrodes is a transparent electrode.

3. An apparatus according to claim 1, wherein the counter substrate has formed thereon a black matrix for covering an area expect for an area above the common electrode.

4. An apparatus according to claim 1, wherein the common electrode is extended to cover an area above each source bus line so as to shied the pixel electrodes from the source bus lines, and the pixel electrodes are extended to cover an area above the source bus lines.

5. A method of producing a transistor array substrate used for a liquid crystal display apparatus in which a liquid crystal layer is sandwiched between the transistor array substrate and a counter substrate, comprising the steps of;

(a) forming gate bus lines on a transparent insulating substrate;

(b) forming a first insulating layer on the substrate formed in the step (a);

(c) forming source bus lines on the first insulating layer;

(d) forming a second insulating layer on the substrate formed in the step (c);

(e) forming a common electrode on the second insulating layer in a direction parallel to the gate bus line direction to cover an area above which pixel electrodes are to be later formed and an area above the source bus lines;

(f) forming a matrix array of thin film transistors each including a semiconductor layer and an impurity-doped semiconductor layer on the substrate formed in the step (e) through a third insulating layer; and

(g) forming source electrodes and drain electrodes for the thin film transistors, and forming the pixel electrodes each extending from a corresponding one of the drain electrodes, and wherein an auxiliary capacitor is constituted between said common electrode and each of the pixel electrodes through the third insulating layer.

6. A method of producing a transistor array substrate used for a liquid crystal display apparatus in which a liquid crystal layer is sandwiched between the transistor array substrate and a counter substrate, comprising the steps of;

(a) forming gate bus lines on a transparent insulating substrate;

(b) forming a first insulating layer on the substrate formed in the step (a);

(c) forming a common electrode on the first insulating layer in a direction perpendicular to the gate bus line direction to cover an area above which pixel electrodes are to be later formed and an area above the source bus lines;

(d) forming a matrix array of thin film transistors each including a semiconductor layer and an impurity-doped semiconductor layer on the substrate formed in the step (c) through a second insulating layer; and

(g) forming source electrodes and drain electrodes for the thin film transistors, and forming the pixel electrodes each extending from a corresponding one of the drain electrodes, and wherein an auxiliary capacitor is constituted between said common electrode and each of the pixel electrodes through the second insulating layer.