Semiconductor memory device having a memory test circuit
First Claim
1. A semiconductor memory device having a function of testing its own operation through a parallel access to memory cells, comprising:
- a plurality of examined memory cells for storing data to be tested in a test mode of the device, said plurality of examined memory cells being arranged in rows and columns;
a plurality of reference memory cells in a column for storing expected data in the test mode;
a plurality of word lines which are connected with the examined memory cells in respective rows and respective ones of said plurality of reference memory cells;
a plurality of pairs of bit lines operating complementarily, connected with the examined memory cells in respective columns;
a pair of bit lines operating complementarily, connected with said plurality of reference memory cells in a single column;
a plurality of sense amplifiers connected with respective pairs of bit lines connected with the examined memory cells and the reference memory cells for amplifying data on the bit lines before the data are outputted;
a line data memory circuit for outputting the expected data written to a reference memory cell via the pair of bit lines connected to the reference memory cell;
a bit line select circuit for selecting, in response to the expected data, one of the bit lines for each of the examined memory cells when the expected data is of a low level, and selecting the other of the bit lines when the expected data is of a high level;
a plurality of output evaluation circuits connected with respective ones of the pairs of bit lines for the examined memory cells, each output evaluation circuit detecting via the one bit line selected by the bit line select circuit when the expected data is of a low level, an output signal from the corresponding examined memory cell which expresses data having been written to the examined memory cell in parallel to the reference memory cell and which ought to have a value identical with the expected data; and
detecting the output signal via the other bit line selected by the bit line select circuit when the expected data is of a high level; and
outputting a signal indicative of coincidence or non-coincidence between the output signal detected and the expected data.
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Accused Products
Abstract
A semiconductor memory device has an array of examined memory cells, and reference memory cells in a column. The examined memory cells in each column and the reference memory cells are connected with respective pairs of complementary bit lines connected with sense amplifiers. Each reference memory cell and the examined memory cells in each row are connected with corresponding word lines. The device also has a line data memory circuit, a bit line select circuit and a plurality of output evaluation circuits connected with the bit line pairs for the examined memory cells. In a test mode, identical data is simultaneously written to the reference and examined memory cells connected with each word line. The line data memory circuit outputs data from the reference memory cell as expected data, in response to which, the bit line select circuit selects one of the bit lines for each of the examined memory cells when the expected data is LOW, and the other of the bit lines when the expected data is HIGH. Each output evaluation circuit simultaneously detects an output from a corresponding examined memory cell via the one bit line or the other bit line selected in accordance with the expected data, and outputs a signal indicating coincidence or non-coincidence between the output signal detected and the expected value. Thus the device tests its own operation through a parallel access to the memory cells.
49 Citations
11 Claims
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1. A semiconductor memory device having a function of testing its own operation through a parallel access to memory cells, comprising:
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a plurality of examined memory cells for storing data to be tested in a test mode of the device, said plurality of examined memory cells being arranged in rows and columns; a plurality of reference memory cells in a column for storing expected data in the test mode; a plurality of word lines which are connected with the examined memory cells in respective rows and respective ones of said plurality of reference memory cells; a plurality of pairs of bit lines operating complementarily, connected with the examined memory cells in respective columns; a pair of bit lines operating complementarily, connected with said plurality of reference memory cells in a single column; a plurality of sense amplifiers connected with respective pairs of bit lines connected with the examined memory cells and the reference memory cells for amplifying data on the bit lines before the data are outputted; a line data memory circuit for outputting the expected data written to a reference memory cell via the pair of bit lines connected to the reference memory cell; a bit line select circuit for selecting, in response to the expected data, one of the bit lines for each of the examined memory cells when the expected data is of a low level, and selecting the other of the bit lines when the expected data is of a high level; a plurality of output evaluation circuits connected with respective ones of the pairs of bit lines for the examined memory cells, each output evaluation circuit detecting via the one bit line selected by the bit line select circuit when the expected data is of a low level, an output signal from the corresponding examined memory cell which expresses data having been written to the examined memory cell in parallel to the reference memory cell and which ought to have a value identical with the expected data; and
detecting the output signal via the other bit line selected by the bit line select circuit when the expected data is of a high level; and
outputting a signal indicative of coincidence or non-coincidence between the output signal detected and the expected data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A test circuit for a semiconductor memory device comprising:
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a means for generating an expected value of either high or low level; an output signal line for temporarily holding the expected value; a fail signal line for constantly holding a level in reverse phase to the output signal line; a first data line carrying a first data signal of a level which should be identical to that of the expected value; a second data line carrying a second data signal which is a complementary signal of the first data signal; a data signal select circuit for, in response to the expected value from the generating means, generating a data select signal designating either the first data signal or the second data signal based on the expected value; a first switch for selecting and outputting one of the complementary first and second data signals in response to the data select signal generated by the data signal select circuit; a second switch provided between the output signal line and the fail signal line so that in response to an output signal from the first switch the second switch electrically connects the output signal line with or separates the output signal line from the fail signal line in accordance with a level of the output signal; wherein whenever the level of the first data signal is coincident with the level of the expected value, the output signal from the first switch allows the second switch to separate the output signal line from the fail signal line so that the output signal line outputs the expected value temporarily held by the output signal line, and whenever the level of the first data signal is not coincident with the level of the expected value, the output signal from the first switch causes the second switch to connect the output signal line with the fail signal line so that the output signal line outputs the level held by the fail signal line. - View Dependent Claims (11)
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Specification