Synchronous optical transmission system

• US 5,185,736 A
• Filed: 05/12/1989
• Issued: 02/09/1993
• Est. Priority Date: 05/12/1989
• Status: Expired due to Fees

• Current Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Smith, Joseph L., Peters, Richard, Williams, Timothy J., Jones, Jeffrey P., Yaemsiri, Jak, Sutton, Michael, Sanders, Richard J. Jr., Dunning, Stephen C., Tyrrell, Raymond E., Stoia, Kenneth J., Thorne, Hal A., Farrell, Patrick M., Stephenson, William H., Abu-Saba, Camille A., Runyon, V. Paul, Merrill, Dana, Briscoe, M. Rodney, Wilkerson, Victor W., Sanders, Gus C., Bernhardt, Keith, Arani, Mohammad S., Rou, Wenkwei, Sonnenberg, Heinrich T., Bishop, O. Lamar, Fox, William J., Weeber, William B., Czerwiec, Richard M., Sutherland, Joseph E., Hurlocker, Claude M., Baydar, Ertugrul, Powell, William E., Krisher, Dale L., Gingell, Michael J., Noser, Francis G.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Marcelo, Melvin
• Application Number:
  US07/351,861
• Time in Patent Office: 1,369 Days
• Field of Search: 370/84, 370/4, 370/3, 370/55, 370/68, 455/600, 455/606, 455/607, 455/609, 455/613, 455/617, 455/618, 455/619
• US Class Current: 370/358
• CPC Class Codes: H04J 2203/0048 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04J 2203/006 Fault tolerance and recovery
• CPC Class Codes: H04J 3/08 Intermediate station arrangements, e.g. for branching, for tapping-off
• CPC Class Codes: H04J 3/1611 Synchronous digital hierarchy [SDH] or SONET H04J3/1664 takes precedence for interactions with OTN

Abstract

A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Claims

1. A synchronous optical transmission system for interfacing with high speed communication channels conforming to the synchronous optical network (SONET) standard so as to convey information to and from said high speed channels operating at different transmission rates, as well as to and from at least one said high speed channel and lower speed channels conforming to other communication standards comprising:

A) a fiber transmission system (FTS) having;

1) means for interfacing to a communication medium operating at a first SONET high speed channel transmission rate;

2) means for interfacing to a second communication medium comprising a plurality of channels, each operating at a lower transmission rate than the first SONET high speed channel; and

3) means for multiplexing said lower transmission rate channels to the first SONET channel as well as for demultiplexing the first SONET channel to the lower channels;

B) a terminal multiplexer (TM) having;

1) a means for interfacing to a SONET high speed channel;

2) a time slot multiplexer (TSM) having a lower speed output, the TSM interconnected to said interfacing means for cross-connecting lower speed channels to and from the SONET high speed channel at the lower speed output of the time slot multiplexer;

3) lower speed channel interfacing means connected to the lower speed output of the TSM for interfacing the lower speed output of the TSM with lower speed channels including means for reformatting the data of the lower speed channel so as to be compatible with the higher speed channel and for converting the formatting of the higher speed channel to the format of the lower speed channel; and

4) means for controlling the cross-connect function of the TSM; and

C) an add/drop multiplexer (ADM) comprising;

1) first means for interfacing to a SONET high speed channel at a first location,

2) a time slot multiplexer (TSM) having a lower speed output, the TSM interconnected to said add/drop multiplexing interfacing means for cross-connecting lower speed channels to and from the SONET high speed channel and a second SONET high speed channel as well as to and from the lower speed output of the TSM;

3) a lower speed channel interfacing means connected to the lower speed output of the TSM for interfacing the lower speed output of the TSM with lower speed channels including means for reformatting the data of the lower speed channel so as to be compatible with the higher speed channel and for converting the formatting of the higher speed channel to the format of the lower speed channel;

4) second means for interfacing to a SONET high speed channel at a second location; and

5) means for controlling the cross-connect function of the TSM.

2. A synchronous optical transmission system as defined in claim 1, wherein the FTS, TM and ADM each further incorporate a craft orderwire alarm (COA) unit respectively interconnected to the interfacing means and multiplexing means of the FTS, to the interfacing means, lower speed channel interfacing means, TSM and the cross-connect controlling means of the TM, and to the first and second interfacing means, lower speed channel interfacing means, TSM and cross-connect controlling means of the ADM, for conveying craft orderwire and alarm information to and from the associated FTS, TM and ADM respectively.

3. A synchronous optical transmission system as defined in claim 2, wherein the TSM has means for removing one or more lower speed channels from a SONET high speed channel and for adding one or more lower speed channels to a SONET high speed channel as well as means for interconnecting lower speed channels interfaced with the first interface means to a SONET high speed channel interfaced to the second interface means, and wherein the ADM includes a network controller interconnected with the TSM for directing the adding and removing of lower speed channels by the TSM with respect to the SONET high speed channels, wherein the ADM comprises a watchdog timer for monitoring the performance of the microprocessor forming part of the network controller and wherein the COA for the ADM comprises reprovisioning means for sensing the timeout status of the watchdog timer so as to reprovision selected lower speed channels within the TSM when a watchdog timeout is detected, thereby connecting selected lower speed channels from the first interface means to the second interface means.

4. A synchronous optical transmission system as defined in claim 1, wherein the FTS, TM and ADM further comprise modules forming at least portions of the means and TSM defining the FTS, TM and ADM, and also comprises serial busses connected between modules thereof, wherein the format of the data conveyed on these serial busses is of a serial transport frame format such that the data is transferred in frames where each frame comprises N channels, where N is an integer greater than one, and wherein each channel has a fixed length of bits, and further wherein for each of M of said N channels, where M is an integer less than N, means for placing data, representing information to be conveyed, in one portion of the channel;

for each of said M channels, means for placing control information related to the data in that channel in a second portion of the channel; and

means for placing synchronization data in at least one channel of each frame, and further comprising means connected to said serial busses for generating serial data in said serial transport frame format.

5. A synchronous optical transmission system as defined in claim 1, wherein the FTS, TM and ADM interfaces to the SONET high speed channels further comprise means for scrambling said data to be placed on the communication medium as well as for scrambling said data to be received from said communication medium, wherein said scrambling function is performed by a parallel scrambling circuit which emulates a serial pseudo-random generator which generates a serial output such that the next serial output value is based upon an Exclusive OR combination of at least two preceding serial output values, the maximum preceding serial output value defined as the Pth preceding serial output value, where P is an integer greater than one;

the parallel scrambling circuit comprising;

1) W latches, where W is an integer equal to or greater than P, each latch having an output having a logic value 1 or 0, the latched outputs designated Q0 to Q(W-1), each output for each latch i, where i is an integer from 0 to W-1, representing the next time sequential output of the serial pseudo-random generator so that the parallel composite latch outputs Q0 to Q(W-1) are the same as the serial pseudo-random generator output sequence for W successive outputs, each latch also having an input operated upon receipt of a clock signal for receipt of data for controlling the next logic value on the latch output;

2) W Exclusive OR gates, each having at least two inputs and one output, each Exclusive OR gate output connected to a corresponding input of one latch so as to define the next value of the latch output upon receipt of the next clock signal;

3) means for connecting each input of each Exclusive OR gate to one latch output Qi so that the output of each Exclusive OR gate represents the corresponding next value of the latch to which this Exclusive OR gate output is connected; and

4) means connected to the latch outputs for Exclusive OR for combining the latch outputs with the data to be scrambled.

6. A synchronous optical transmission system as defined in claim 1, wherein the TM and the ADM further incorporate a parallel frame synchronization circuit for detecting known frame synchronization information having a length of P bits, where P is an integer greater than one and at least equal to N, where N is an integer greater than one, the frame synchronization information denoting the presence of a frame of data, wherein the frame of data comprises a serial bit stream of data of frequency (f_in), the frame of data comprising more than P bits with the bits arranged in units of data, each unit of data comprising a fixed number of bits, the frame synchronization information also denoting the boundary between units of said data, comprising:

1) a serial to parallel convertor for converting the incoming serial bit stream into parallel data words, each word comprising N bits, said parallel data words occurring at a frequency, f_pdw, equal to f_in /N;

2) means for receiving the parallel data words from the serial to parallel convertor so as to present their output values on at least Q +0 R - 1 parallel output lines, where Q is an integer having a permissible range of values as set forth in element C) and R is an integer with a minimum value as set forth in element C), said receiving means receiving at least the truncated integer value of {(2Q/N) +1 (+1 if (2Q/N) has a remainder)}sequential parallel data words;

3) at least R addressable detectors, where R is an integer at least equal to N times the sum of the truncated integer value of the quotient of the frequency of the parallel data words (f_pdw) divided by the frequency at which detector comparisons are made (f_dc), plus one (plus one if f_pdw /f_dc has a remainder), that is, R = N ×

{truncated[f_pdw /f_dc ] + 1 (+1 if f_pdw /f_dc has a remainder)}, each detector having Q inputs, where Q is equal to at least R but not greater than P if P is >

N, the Q inputs of each detector connected to Q parallel output lines of the receiving means so that for each detector i, where i is an integer from 2 to Q, Q -1 inputs are connected to the same parallel output lines as detector i -1, so that the Q detectors span the 2Q -1 parallel output lines of the receiving means, and further wherein each detector comprises means for determining at the detector comparison frequency (f_dc) if the incoming data bits from the receiving means parallel output lines correspond to at least a portion of the known frame synchronization information so as to generate an output if a comparison is made; and

4) means interconnected to each detector for receipt of the address of the detector that generated a comparison output, said means also connected to the Q + R -1 parallel output lines of the receiving means for generating a parallel output of data aligned with the boundary of said units of data.

7. A synchronous optical transmission system as defined in claim 1, wherein the interface means between the high speed SONET channel and the respective FTS, TM and ADM lower speed channels incorporate circuitry which operates at a clock frequency less than that of the high speed data stream, wherein said lower speed circuitry operates in parallel upon a plurality of data bits, wherein said circuitry further comprises a transfer strobe delay stage selector for insuring the accurate transfer of data between the high speed data stream associated with the high speed circuitry and a low speed parallel data stream associated with the low speed circuitry comprising:

1) means for periodically inserting a synchronization channel comprising N +1 bits of data of a predetermined bit pattern into the high speed stream of data, where N is a positive integer;

2) means for converting the high speed stream of data and periodic synchronization channel into words of parallel data, each word of parallel data containing N +1 bits;

3) means for generating a periodic latch signal having a repetition rate equal to the high speed bit transfer rate divided by N +1;

4) a delay stage module for receipt of the latch signal, the delay stage module comprising a plurality of delay stages, each stage having a time delay between its input and its output, each stage having a selectable output, and each stage, except the last stage, connected as an input to the next stage;

5) means for selecting any one of the delay stage outputs of the delay stage module so as to generate a transfer strobe signal having a repetition rate the same as the latch signal, but time delayed equal to the sum of the time delays of the selected delay stage plus all the preceding delay stages;

6) a synchronization channel identification module for receipt of the parallel data generated by the serial to parallel converting means and operable so as to perform an identification process upon receipt of the transfer strobe signal, the synchronization identification module having means for generating an "in sync" signal on an output when a word of parallel data periodically matches a predetermined parallel data bit pattern;

wherein the periodic matching occurs at the same rate as the periodicity of the synchronization channel, thereby effectively determining the proper detection of the periodic synchronization channel; and

7) a delay stage control module connected to said output of the synchronization channel identification module for causing the delay stage selecting means to change the delay stage selected if an "in-sync" signal is not received by the delay stage control circuit, and wherein modification of the selected delay stage is halted if an "in-sync" signal is received.

8. A synchronous optical transmission system as defined in claim 1, wherein the plurality of channels associated with the second communication medium each comprise a SONET channel operating at a lower transmission rate than the first SONET channel.

9. A parallel pseudo-random generator as defined in claim 5, wherein the next serial output value based upon an Exclusive OR combination of at least two preceding serial output values is defined by a polynomial of the form 1+ x^M + . . . + x^P, where M is a positive integer less than P, so that any stage "n" of the serial pseudo-random generator, where n is an integer, is defined by the identity Q(n) ≡

Q(n + M) + . . . +Q(n + P), and wherein the means for connecting each input of each Exclusive OR gate to one latch output Qi comprises determination of the relationship of each next output Qi based upon the present outputs Q0 through Q(W -1) by determining the relationship of Q(i - W), which is equivalent to the next output of Qi, and then successively applying the serial pseudo-random generator identify for a value of n equal to i - W until the righthand portion of the identity only represents latch outputs from the group of latch output comprising Q0 to Q(W -1).

10. A parallel pseudo-random generator as defined in claim 9, further wherein the means for connecting each input of each Exclusive OR gate to one latch output Qi comprises elimination of Exclusive OR combinations of the type Qj + Qj, for any integer value of j from 0 to W -1.

11. A synchronous optical transmission system as defined in claim 1, wherein the FTS, TM and ADM interfaces to the SONET high speed channels further comprise means for scrambling said data to be placed on the communication medium as well as for descrambling data to be received from said communication medium, wherein said scrambling function is performed by a parallel scrambling circuit which emulates a serial pseudo-random generator which generates a serial output such that the next serial output value is based upon an Exclusive OR combination of at least two preceding serial output values, the maximum preceding serial output value defined as the Pth preceding serial output value, where P is an integer greater than one, wherein the next serial output value is defined by a polynomial of the form 1+ x^M + . . . + x^P, where M is a positive integer less than P, so that any stage "n" of the serial pseudo-random generator, where n is an integer, is defined by the identity Q(n) ≡

Q(n + M) + . . . +Q(n + P), the parallel scrambler circuit being executed on W parallel data lines, where W is an integer equal to or greater than P, the parallel scrambler circuit comprising;

A) W latches, each latch having an output having a logic value 1 or 0, the latched outputs designated Q0 to Q(W -1), each output for each latch i, wherein i is an integer from 0 to W -1, representing the next time sequential output of the serial pseudo-random generator so that the parallel composite latch outputs Q0 to Q(W -1) are the same as the serial pseudo-random generator output sequence for W successive outputs, each latch also having an input operated upon receipt of a clock signal for receipt of data for controlling the next logic value on the latch output;

b) W Exclusive OR gates, each having at least two inputs and one output, each Exclusive OR gate output connected to a corresponding input of one latch so as to define the next value of the latch output upon receipt of the next clock signal;

C) means for connecting each input of each Exclusive OR gate to one latch output Qi so that the output of each Exclusive OR gate represents the corresponding next value of the latch to which this Exclusive OR gate output is connected, wherein said means comprises determination of the relationship of each next output Qi based upon the present outputs Q0 through Q(W -1) by determining the relationship of Q(i - W), which is equivalent to the next output of Qi, and then successively applying the serial pseudo-random generator identity for a value of n equal to i - W until the righthand portion of the identity only represents latch outputs from the group of latch outputs comprising Q0 to Q(W -1); and

D) a second set of W Exclusive OR gates each having one input connected to one latch output and a second input connected to one of the W data lines, the output of each said Exclusive OR gate representing the pseudo-random scrambled version of the data on the corresponding data line.

12. A parallel pseudo-random generator scrambler as defined in claim 11, wherein the serial Exclusive OR combination defining the serial pseudo-random generator determines its next output value based upon the sixth and seventh preceding serial output values (P =7).

13. A parallel pseudo-random generator scrambler as defined in claim 12, wherein the number of latches is eight, the latches having corresponding outputs Q0 through Q7, and wherein the corresponding Exclusive OR gates Ex0-Ex7 each have their output connected to the corresponding latch input, and having their inputs connected to the following latch outputs:

Ex0 inputs connected to Q4 and Q6

Ex1 inputs connected to Q5 and Q7

Ex2 inputs connected to Q0 and Q1

Ex3 inputs connected to Q1 and Q2

Ex4 inputs connected to Q2 and Q3

Ex5 inputs connected to Q3 and Q4

Ex6 inputs connected to Q4 and Q5

Ex7 inputs connected to Q5 and Q6.

14. A synchronous optical transmission system as defined in claim 1, wherein the TM and the ADM further incorporate a parallel frame synchronization circuit for detecting known frame synchronization information having a length of P bits, where P is an integer greater than one, the frame synchronization information denoting the presence of a frame of data, wherein the frame of data comprises a serial bit stream of data of frequency (f_in), the frame synchronization information forming part of a serial bit stream of data having a frequency f_in, comprising:

A) a serial to parallel converter for converting the incoming serial bit stream into parallel data words, each word comprising N bits, where N is an integer greater than 1;

B) means for receiving the parallel data words from the serial to parallel converter so as to present their output values on a plurality of parallel output lines;

C) a plurality of detectors, each detector having a third plurality of inputs so that the plurality of detector inputs span the parallel output lines of the receiving means, wherein each detector comprises means for determining if the data presented at its third plurality of inputs corresponds to at least a portion of the frame synchronization information so as to generate an output if a comparison is made; and

D) means interconnected to each detector and to the parallel output lines of the receiving means for generating parallel output data aligned with the detection location of the frame synchronization information.

15. A parallel frame synchronization circuit as defined in claim 14, further comprising a second group of detectors for detecting a second portion of the frame synchronization information after detection of a first portion of the frame synchronization information by the first second plurality of detectors, the second group of detectors connected to the parallel output lines of the receiving means in the same manner as the first detectors, and wherein the means for generating a parallel output of data does not generate such a output of data until both the first and second portions of the frame synchronization information are detected.

16. A parallel frame synchronization circuit as defined in claim 14, wherein the frame synchronization information comprises at least first and second time adjacent portions having the same information and wherein the parallel frame synchronization further comprises a fourth plurality of flip-flops, each having an input connected to an output of one of the second plurality of detectors and each having an output which reflects the state of its input one clock cycle earlier, and further comprising means for receipt of the output of each flip-flop and each output of each detector, the output of said logic means interposed between each detector and the means for generating the parallel output of data aligned with the boundary of the units of data so that frame synchronization is determined when the adjacent portions of the frame synchronization information are detected by the detector and flip-flop consecutively.

17. A synchronous optical transmission system as defined in claim 7, wherein the transfer strobe delay stage further comprises:

8) a second, auxiliary, means for independently selecting any one of the time delay stage outputs of the delay stage module so as to generate an auxiliary transfer strobe signal;

9) a second, auxiliary, synchronization channel identification module for receipt of the parallel data generated by the serial to parallel converting means and operable so as to perform an identification process upon receipt of the auxiliary transfer strobe signal, the auxiliary synchronization identification module having means for generating an "in sync" signal on an output when a word of parallel data periodically matches a predetermined parallel data bit pattern;

wherein the periodic matching occurs at the same rate as the periodicity of the synchronization channel, thereby effectively determining the proper detection of the periodic synchronization channel;

10) a second, auxiliary, delay stage control module connected to the output of the second synchronization channel identification module for causing the auxiliary delay stage selecting means to determine an optimal delay stage for synchronization channel detection; and

11) means for dynamically adjusting the selected delay stage of the delay stage selecting means associated with the transfer strobe once synchronization channel detection has occurred if the selected delay stage varies from the selected auxiliary delay stage by more than a predetermined amount.

18. A synchronous optical transmission system as defined in claim 1, wherein the FTS, TM and ADM further comprise modules forming at least portions of the means and TSM defining the FTS, TM and ADM, and also comprises serial busses connected between modules thereof, wherein the format of the data conveyed on these serial busses is of a serial transport frame format for positioning data to be transferred in a serial bit stream, wherein means are associated with each of these serial busses so as to arrange the data to be transferred in a plurality of frames, where each frame comprises N channels, each having a fixed length of bits, where N is an integer greater than 1, means for each of M of said N channels and at least some of the plurality of frames, where M is an integer greater than 0 and less than N, for placing data representing information to be conveyed, in one portion of the channel, means for each of said M channels, for placing control information related to the data in that channel, in a second portion of the channel, and means for placing synchronization data in at least one channel of each frame.

19. A synchronous optical transmission system for interfacing with high speed communication channels conforming to the synchronous optical network (SONET) standard so as to convey information to and from said high speed channels operating at different transmission rates, as well as to and from at least one said high speed channel and lower speed channels conforming to other communication standards comprising:

A) a fiber transmission system (FTS) having;

1) means for interfacing to a communication medium operating at a first SONET high speed channel transmission rate;

2) means for interfacing to a second communication medium comprising a plurality of channels, each operating at a lower transmission rate than the first SONET high speed channel; and

3) means for multiplexing said lower transmission rate channels to the first SONET channel as well as for demultiplexing the first SONET channel to the lower channels; and

B) a terminal multiplexer (TM) having;

1) means for interfacing to a SONET high speed channel;

2) a time slot multiplexer (TSM) having a lower speed output, the TSM interconnected to said interfacing means for cross-connecting lower speed channels to and from the SONET high speed channel at the lower speed output of the time slot multiplexer;

3) lower speed channel interfacing means connected to the lower speed output of the TSM for interfacing the lower speed output of the TSM with lower speed channels including means for reformatting the data of the lower speed channel so as to be compatible with the higher speed channel and for converting the formatting of the higher speed channel to the format of the lower speed channel; and

4) means for controlling the cross-connect function of the TSM.

20. A synchronous optical transmission system for interfacing with high speed communication channels conforming to the synchronous optical network (SONET) standard so as to convey information to and from said high speed channels operating at different transmission rates, as well as to and from at least one said high speed channel and lower speed channels conforming to other communication standards comprising:

A) a fiber transmission system (FTS) having;

1) means for interfacing to a communication medium operating at a first SONET high speed channel transmission rate;

2) means for interfacing to a second communication medium comprising a plurality of channels, each operating at a lower transmission rate than the first SONET high speed channel; and

3) means for multiplexing said lower transmission rate channels to the first SONET channel as well as for demultiplexing the first SONET channel to the lower channels; and

B) an add/drop multiplexer (ADM) comprising;

1) first means for interfacing to a SONET high speed channel at a first location,

2) a time slot multiplexer (TSM) having a lower speed output, the TSM interconnected to said add/drop multiplexing interfacing means for cross-connecting lower speed channels to and from the SONET high speed channel and a second SONET high speed channel as well as to and from the lower speed output of the TSM;

3) a lower speed channel interfacing means connected to the lower speed output of the TSM for interfacing the lower speed output of the TSM with lower speed channels including means for reformatting the data of the lower speed channel so as to be compatible with the higher speed channel and for converting the formatting of the higher speed channel to the format of the lower speed channel;

4) second means for interfacing to a SONET high speed channel at a second location; and

5) means for controlling the cross-connect function of the TSM.

21. A synchronous optical transmission system for interfacing with high speed communication channels conforming to the synchronous optical network (SONET) standard so as to convey information to and from said high speed channels, as well as to and from at least one said high speed channel and lower speed channels conforming to other communication standards comprising:

A) a terminal multiplexer (TM) having;

1) means for interfacing to a SONET high speed channel;

2) a time slot multiplexer (TSM) having a lower speed output, the TSM interconnected to said interfacing means for cross-connecting lower speed channels to and from the SONET high speed channel at the lower speed output of the time slot multiplexer;

3) lower speed channel interfacing means connected to the lower speed output of the TSM for interfacing the lower speed output of the TSM with lower speed channels including means for reformatting the data of the lower speed channel so as to be compatible with the higher speed channel and for converting the formatting of the higher speed channel to the format of the lower speed channel; and

4) means for controlling the cross-connect function of the TSM; and

B) an add/drop multiplexer (ADM) comprising;

2) first means for interfacing to a SONET high speed channel at a first location,

2) a time slot multiplexer (TSM) having a lower speed output, the TSM interconnected to said add/drop multiplexing interfacing means for cross-connecting lower speed channels to and from the SONET high speed channel and a second SONET high speed channel as well as to and from the lower speed output of the TSM;

3) a lower speed channel interfacing means connected to the lower speed output of the TSM for interfacing the lower speed output of the TSM with lower speed channels including means for reformatting the data of the lower speed channel so as to be compatible with the higher speed channel and for converting the formatting of the higher speed channel to the format of the lower speed channel;

4) second means for interfacing to a SONET high speed channel at a second location; and

5) means for controlling the cross-connect function of the TSM.