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High speed data communication system using phase shift key coding

  • US 5,185,765 A
  • Filed: 07/23/1990
  • Issued: 02/09/1993
  • Est. Priority Date: 05/08/1986
  • Status: Expired due to Fees
First Claim
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1. An encoder apparatus for use in a high speed data transmission system for transmitting an input NRZ signal over a communications path as a data signal, said NRZ signal representing a series of binary data bits of "1" and "0" polarities clocked at a given clock rate, comprising:

  • polarity change detecting means responsive to said NRZ signal for detecting whether a current data bit of said NRZ signal has the same or a changed polarity as a previous data bit, wherein each data bit of said NRZ signal has a bit period of M clock periods;

    counting means for maintaining a count of the number of polarity changes of the data bits in each encoding cycle defined from a beginning reset point of said NRZ signal;

    encoding means for encoding an encoded signal representing said NRZ signal, said encoded signal having a waveform which switches between two opposing polarities with each polarity change of the data bits in each encoding cycle, wherein the polarity of the encoding signal is switched with widths of M/M, M+1/M, and M+2/M bit periods after a previous polarity switch depending upon whether a polarity change is detected by said polarity change detecting means and the count maintained by said counting means, as follows;

    (1) a width of M/M when a current data bit is the same as a previous data bit (no polarity change);

    (2) a width of M+1/M when a current data bit has a polarity that is changed from that of a previous data bit, the count of said counting means being thereupon indexed by one;

    (3) a width of M+2/M when a current data bit has a polarity that is changed from that of a previous data bit and the count of said counting means including the current polarity change is equal to M-1 and a 101 bit pattern is present in the data stream to the encoding means, the count of said counting means being thereupon reset to define the beginning reset point for the next encoding cycle,wherein, in all of the above said means, M is a positive even integer greater than 3.

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