Neuron unit and neuron unit network

• US 5,185,851 A
• Filed: 03/24/1992
• Issued: 02/09/1993
• Est. Priority Date: 07/12/1989
• Status: Expired due to Term

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Horiguchi, Kiroyuki, Eguchi, Hirotoshi, Furuta, Toshiyuki
• Primary Examiner(s): MacDonald, Allen R.
• Application Number:
  US07/856,645
• Time in Patent Office: 322 Days
• Field of Search: 395/24, 395/27
• US Class Current: 706/43
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A neuron unit simultaneously processes a plurality of binary input signals. The neuron unit includes input lines for receiving first and second input signals which undergo transitions with time, first and second memories for storing weighting coefficients, a first gate for successively obtaining a logical product of one of the first input signals and a corresponding one of the weighting coefficients read out from the first memory for each of the first input signals, a second gate for successively obtaining a logical product of one of the second input signals and a corresponding one of the weighting coefficients read out from the second memory for each of the second input signals, a third gate for obtaining a logical sum of logical products output from the first gate, a fourth gate for obtaining a logical sum of logical products output from the second gate, and an output part including an inverter for inverting the logical sum output from the fourth gate and a gate for obtaining one of a logical product and a logical sum of the logical sum output from the third gate and an inverted logical sum output from the inverter. This gate outputs an output signal of the neuron unit.

Claims

1. A neuron unit for simultaneously processing a plurality of binary input signals and for outputting an output signal which is indicative of a result of the processing, said neuron unit comprising:

a plurality of first input lines for receiving first binary input signals which undergo transitions with time;

a plurality of second input lines for receiving second binary input signals which undergo transitions with time;

first and second memory means for storing weighting coefficients;

first gate means for successively obtaining a logical product of one of said first binary input signals received from said first input lines and a corresponding one of the weighting coefficients read out from said first memory means for each of said first binary input signals;

second gate means for successively obtaining a logical product of one of said second binary input signals received from said second input lines and a corresponding one of the weighting coefficients read out from said second memory means for each of said second binary input signals;

third gate means for obtaining a logical sum of logical products output from said first gate means;

fourth gate means for obtaining a logical sum of logical products output from said second gate means; and

output means including an inverter for inverting the logical sum output from said fourth gate means and a gate for obtaining one of a logical product and a logical sum of the logical sum output from said third gate means and an inverted logical sum output from said inverter, said gate outputting an output signal of said neuron unit.

2. The neuron unit as claimed in claim 1 wherein said first and second binary input signals respectively describe a signal quantity in a form of a pulse density, and said first and second memory means stores the weighting coefficients which respectively describe a signal quantity in a form of a pulse density.

3. The neuron unit as claimed in claim 2 wherein each weighting coefficient has a pulse density defined by a number of first values and second values within a predetermined time, the first values and second values are arranged at random, and the first and second values respectively correspond to high and low binary signal levels.

4. The neuron unit as claimed in claim 1 wherein said first and second memory means respectively include shift registers each having a storage capacity of at least two bits.

5. The neuron unit as claimed in claim 4 wherein said first and second memory means respectively use a content of each shift register recursively.

6. The neuron unit as claimed in claim 1 wherein said first input lines, said first memory means, said first gate means and said third gate means form an excitation group, and said second input lines, said second memory means, said second gate means and said fourth gate means form an inhibition group.

7. A neuron unit network comprising:

a plurality of neuron units which are coupled to form a hierarchical structure which has a plurality of layers; and

a plurality of signal lines coupling outputs of arbitrary neuron units in one layer of the hierarchical structure to inputs of arbitrary neuron units in another layer of the hierarchical structure,

each of said neuron units simultaneously processing a plurality of binary input signals and outputting an output signal which is indicative of a result of the processing,

said neuron unit comprising a plurality of first input lines for receiving first binary input signals which undergo transitions with time, a plurality of second input lines for receiving second binary input signals which undergo transitions with time, first and second memory means for storing weighting coefficients, first gate means for successively obtaining a logical product of one of said first binary input signals received from said first input lines and a corresponding one of the weighting coefficients read out from said first memory means for each of said first binary input signals, second gate means for successively obtaining a logical product of one of said second binary input signals received from said second input lines and a corresponding one of the weighting coefficients read out from said second memory means for each of said second binary input signals, third gate means for obtaining a logical sum of logical products output from said first gate means, fourth gate means for obtaining a logical sum of logical products output from said second gate means, and output means including an inverter for inverting the logical sum output from said fourth gate means and a gate for obtaining one of a logical product and a logical sum of the logical sum output from said third gate means and an inverted logical sum output from said inverter, said gate outputting an output signal of said neuron unit.

8. The neuron unit network as claimed in claim 7 wherein said first and second binary input signals respectively describe a signal quantity in a form of a pulse density, and said first and second memory means stores the weighting coefficients which respectively describe a signal quantity in a form of a pulse density.

9. The neuron unit network as claimed in claim 8 wherein each weighting coefficient has a pulse density defined by a number of first values and second values within a predetermined time, the first values and second values are arranged at random, and the first and second values respectively correspond to high and low binary signal levels.