Arithmetic and logic processing unit for computer graphics system

• US 5,185,856 A
• Filed: 03/16/1990
• Issued: 02/09/1993
• Est. Priority Date: 03/16/1990
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Alcorn, Byron A., Rauchfuss, Brian D., Cherry, Robert W., Coleman, Mark D.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Zimmerman, Mark K.
• Application Number:
  US07/495,005
• Time in Patent Office: 1,061 Days
• Field of Search: 364/518, 364/521, 364/736, 364/742, 364/754, 364/764, 364/768, 364/146, 395/130, 395/162, 395/164, 395/131
• US Class Current: 345/561
• CPC Class Codes: G06T 15/80 Shading

Abstract

Pixel arithmetic and logical units for rendering pixels in graphics systems. Circuits for performing arithmetic operations on raster scan data are provided. The circuits comprise opcode registers for selecting an arithmetic function which transforms pixel value data corresponding to graphics primitives, multiplication circuits interfaced with the opcode registers for multiplying graphics operators with graphics data to obtain transform pixel value data, combining circuits interfaced with the multiplication circuits for adding transform pixel value data to existing pixel value data and processing circuitry interfaced with the combining circuitry for storing overflow data from the combining circuitry when adding transform pixel data overflows the combining circuitry.

Claims

1. A circuit for performing arithmetic operations on raster scan graphics data, comprising:

opcode means for selecting an arithmetic function;

data source means for providing graphics data;

bus means for bussing data from said data source means;

a blend register for storing a blend factor;

an alpha register for storing an alpha value;

a data selector coupled to said blend register and said alpha register and responsive to said opcode means in selecting between said blend factor and said alpha value and outputting the selected data;

complementing means for complementing the output of said data selector;

multiplication means for multiplying an output of said complementing means with graphics data from said data source means in accordance with an arithmetic function selected by said opcode means to obtain transformed pixel value data;

combining means interfaced with the multiplication means for adding transformed pixel value data to other pixel value data from said data source means; and

processing means interfaced with the combining means for storing overflow data from the combining means when said combining means overflows.

2. The circuit recited in claim 1, wherein said data source means comprises:

pixel alpha port means, coupled to said data selector, for providing antialiased vector data and pixel transparency data to the circuit; and

pixel cache means interfaced with the bus means for providing pixel data to the circuit.

3. The circuit recited in claim 2 wherein the processing means comprises overflow register means for replacing a value in the combining means when circuit operation forces the combining means to generate a carry bit.

4. A data storage device for temporary storage of pixel data in a computer graphics system, comprising:

arithmetic operating means for performing arithmetic raster operations on pixel data;

cache means interfaced with said arithmetic operating means for storing said pixel data, said cache means comprising source cache means for storing pixel data corresponding to pixel locations on a source area, destination cache means for storing pixel data corresponding to pixel locations on a destination area, and pattern cache means for storing pattern or texture map data; and

logic means interfaced with the cache means for performing boolean operations on the pixel, pattern or texture map data.

5. The data storage device recited in claim 4 wherein the source, destination and pattern cache means comprise memory buffers adapted to store data corresponding to 32 pixels on a raster scan display device.

6. The data storage device recited in claim 5 further comprising rotation means interfaced with the source cache means, destination cache means and the pattern cache means for horizontally and vertically aligning pixel data when said pixel data is transferred from said source, destination and pattern cache means to a frame buffer such that said pixel data, when in said frame buffer, will correspond to a prescribed scan line and pixel.

7. The data storage device recited in claim 6 wherein the arithmetic operating means is adapted to perform arithmetic operations on pixel value data one pixel at a time.

8. The data storage device recited in claim 7 further comprising:

a first data bus interfaced with the source cache means for busing source window data to the logic means;

a second data bus interfaced with the destination cache means for busing destination window data to the logic means; and

a third data bus interfaced with the pattern cache means for busing pattern data to the logic means.

9. The data storage device recited in claim 8, further comprising at least one bus which buses data from said cache means to said arithmetic operating means and logic means.

10. The data storage device recited in claim 4 wherein said arithmetic operating means comprises:

opcode means for selecting an arithmetic function;

an alpha register for storing an alpha value;

a blend register for storing a blend factor;

a data selector coupled to said alpha register and said blend register and responsive to said opcode means in selecting between said blend factor and said alpha value and outputting the selected data;

complementing means for complementing the output of said data selector;

multiplication means for multiplying an output of said complementing means with graphics data from said cache means in accordance with an arithmetic function selected by said opcode means to obtain transformed pixel value data;

combining means interfaced with the multiplication means for adding transformed pixel value data to other pixel value data from said cache means; and

processing means interfaced with the combining means for storing overflow data from the combining means when said combining means overflows.

11. The data storage device recited in claim 9 further comprising a blend register interfaced with the bus for storing a blend factor to be used by said arithmetic operating means in transforming data provided by said cache means.