Method to form self-aligned gate structures and focus rings
First Claim
1. A process for the formation of self-aligned gate and focus ring structures around a cold cathode emitter tip, said process comprising the following steps:
- processing a wafer to form at least one conical cathode on a substrate, said cathode having an emitter tip;
depositing a first conformal insulating layer over the surface of the wafer;
depositing a conductive material layer superjacent said first conformal insulating layer;
depositing a second conformal insulating layer superjacent said conductive material layer;
depositing a focus electrode material layer superjacent said second conformal insulating layer;
subjecting the wafer to chemical mechanical planarization (CMP) to expose at least a portion of said conductive material layer; and
etching said layers to expose the emitter tip.
1 Assignment
0 Petitions
Accused Products
Abstract
A selective etching and chemical mechanical planarization process for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a first conformal layer, iii) deposited with a conductive material layer, iv) deposited with a second conformal insulating layer, v) deposited with a focus electrode ring material layer, vi) optionally deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose a portion of the second conformal layer, viii) etched to form a self-aligned gate and focus ring, and thereby expose the emitter tip, afterwhich xi) the emitter tip may be coated with a low work function material.
178 Citations
20 Claims
-
1. A process for the formation of self-aligned gate and focus ring structures around a cold cathode emitter tip, said process comprising the following steps:
-
processing a wafer to form at least one conical cathode on a substrate, said cathode having an emitter tip; depositing a first conformal insulating layer over the surface of the wafer; depositing a conductive material layer superjacent said first conformal insulating layer; depositing a second conformal insulating layer superjacent said conductive material layer; depositing a focus electrode material layer superjacent said second conformal insulating layer; subjecting the wafer to chemical mechanical planarization (CMP) to expose at least a portion of said conductive material layer; and etching said layers to expose the emitter tip.
-
- 2. The process according to claim wherein said first and second conformal insulating layers are selectively etchable with respect to said conductive material layer and said focus electrode layer.
-
14. A process for the formation of self-aligned gate and focus ring structures around a cold cathode tip, said process comprising the following steps:
-
processing a wafer to form at least one conical cathode on a substrate, said cathode having an emitter tip; depositing at least two conformal insulating layers over the tip of said cathode; depositing at least two conductive material layers superjacent said conformal insulating layer; subjecting the wafer to chemical mechanical planarization (CMP); and removing said layers to expose the emitter tip. - View Dependent Claims (15, 16, 17, 18, 19)
-
-
20. A process for the formation of self-aligned gate and focus ring structures around an electron emitting cold cathode tip, said process comprising the following steps:
-
processing a wafer to form at least one cathode having an emitter tip; depositing a first conformal insulating layer over the tip of said cathode; depositing a conductive material layer superjacent said first conformal insulating layer; depositing a second conformal insulating layer superjacent said conductive material layer; depositing a focus electrode material layer superjacent said second conformal insulating layer; subjecting the wafer to chemical mechanical planarization (CMP) to expose at least a portion of said second conformal insulating layer; etching said second conformal insulating layer to create a cavity between said conductive material layer and said focus electrode material layer etching said conductive material layer to form a gate; and removing a portion of said first conformal insulating layer surrounding the tip thereby exposing said tip.
-
Specification