Combined circuit configuration for a CMOS logic inverter and gate

• US 5,187,388 A
• Filed: 10/21/1991
• Issued: 02/16/1993
• Est. Priority Date: 10/21/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Moy, Thomas H.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US07/781,487
• Time in Patent Office: 484 Days
• Field of Search: 307/448, 307/451, 307/445
• US Class Current: 326/49
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

A combined logic circuit includes an inverter and a logic gate that share a common first logic signal. The inverter has an input for receiving the first logic signal and an output for providing an inverted first logic signal. The logic gate has a first input for receiving the first logic signal and two or more secondary inputs for receiving secondary logic signals. The logic gate also includes first and second power supply nodes. The first power supply node receives the inverted first logic signal, thus actively controlling the logic function of the gate as well as eliminating a separate inverting transistor, while the second power supply node normally receives a power supply voltage. The output of the logic gate provides a predetermined logic function of the first and secondary logic signals that is equivalent to the prior art circuit. The combined logic inversion and predetermined logic function are accomplished with one less transistor than prior art circuits.

Claims

1. A logic circuit (20) comprising:

an inverter (M1-M2) having an input for receiving a first logic signal and an output for providing an inverted first logic signal; and

a logic gate (M3-M5, M4-M6) having a first input for receiving the first logic signal, a second input for receiving a second logic signal, a first power supply node for receiving the inverted first logic signal, a second power supply node for receiving a power supply voltage, and an output for providing a logical function of the first and second logic signals, wherein the logic gate includes

a first transistor (M3) of a first polarity type having a gate coupled to the second input, a drain coupled to the output, and a source coupled to the second power supply node;

a second transistor (M4) of a first polarity type having a gate coupled to the first input, a drain coupled to the output, and a source coupled to the second power supply node; and

a third transistor (M5) of a second polarity type having a gate coupled to the second input, a drain coupled to the output, and a source coupled to the first power supply node.

2. A logic circuit as in claim 1 in which the first and second transistors each comprise a P-channel FET, and the third transistor comprises an N-channel FET.

3. A logic circuit (40) comprising:

an inverter (M1-M2) having an input for receiving a first logic signal and an output for providing an inverted first logic signal; and

a logic gate (M3-M5, M4-M6) having a first input for receiving the first logic signal, a second input for receiving a second logic signal, a first power supply node for receiving the inverted first logic signal, a second power supply node for receiving a power supply voltage, and an output for providing a logical function of the first and second logic signals, wherein the logic gate includes

a first transistor (M4) of a first polarity type having a gate coupled to the second input, a drain coupled to the output, and a source coupled to the first power supply node;

a second transistor (M5) of a second polarity type having a gate coupled to the second input, a drain coupled to the output, and a source coupled to the second power supply node; and

a third transistor (M6) of a second polarity type having a gate coupled to first input, a drain coupled to the output, and a source coupled to the second power supply node.

4. A logic circuit (60) comprising:

an inverter (M1-M2) having an input for receiving a first logic signal and an output for providing an inverted first logic signal; and

a logic gate (M3-M7) having a first input for receiving the first logic signal, a second input for receiving a second logic signal, a third input for receiving a third logic signal, a first power supply node for receiving the inverted first logic signal, a second power supply node for receiving a power supply voltage, and an output for providing a logical function of the first, second, and third logic signals.

5. A logic circuit as in claim 4 in which the logical function comprises the logical NAND function.

6. A logic circuit as in claim 4 in which the inverter comprises a CMOS inverter.

7. A logic circuit as in claim 4 in which the logic gate comprises:

a first transistor (M3) of a first polarity type having a gate coupled to the second input, a drain coupled to the output, and a source coupled to the second power supply node;

a second transistor (M4) of a first polarity type having a gate coupled the third input, a drain coupled to the output, and a source coupled to the second power supply node;

a third transistor (M5) of a first polarity type having a gate coupled to the first input, a drain coupled to the output, and a source coupled to the second power supply node;

a fourth transistor (M6) of a second polarity type having a gate coupled to the second input, a drain coupled to the output, and a source; and

a fifth transistor (M7) of a second polarity type having a gate coupled to the third input, a drain coupled to the source of the fourth transistor, and a source coupled to the first power supply node.

8. A logic circuit as in claim 7 in which the first, second, and third transistors each comprise a P-channel FET, and the fourth and fifth transistors each comprise an N-channel FET.

9. A logic circuit (60) comprising:

an inverter (M1-M2) having an input for receiving a first logic signal and an output for providing an inverted first logic signal; and

a logic gate (M3-M7) having a first input for receiving the first logic signal, a plurality of secondary inputs for receiving a plurality of secondary logic signals, a first power supply node for receiving the inverted first logic signal, a second power supply node for receiving a power supply voltage, and an output for providing a logical function of the first and secondary logic signals.

10. A method of inverting a first logic signal and logically combining the first logic signal with a plurality of secondary logic signals, the method comprising the steps of:

providing an inverter having an input and an output;

providing a logic gate having a plurality of inputs, first and second power supply nodes, and an output for providing a predetermined logical combination of the first and secondary logic signals;

coupling the first logic signal to the inverter input and a first input of the logic gate;

coupling the secondary logic signals to corresponding inputs of the logic gate;

coupling the first power supply node of the logic gate to the inverter output; and

coupling the second power supply node of the logic gate to a source of supply voltage.

11. The method of claim 10 further comprising the step of configuring the logic gate to provide a logical NAND function.

12. A logic circuit (20, 40) comprising:

an inverter (M1-M2) having an input for receiving a first logic signal and an output for providing an inverted first logic signal; and

a logic gate (M3-M5, M4-M6) having a first input for receiving the first logic signal, a second input for receiving a second logic signal, a first power supply node for receiving the inverted first logic signal, a second power supply node for receiving a power supply voltage, and an output for providing a logical NAND function of the first and second logic signals.

13. A logic circuit (20, 40) comprising:

an inverter (M1-M2) having an input for receiving a first logic signal and an output for providing an inverted first logic signal; and

a logic gate (M3-M5, M4-M6) having a first input for receiving the first logic signal, a second input for receiving a second logic signal, a first power supply node for receiving the inverted first logic signal, a second power supply node for receiving a power supply voltage, and an output for providing a logical NOR function of the first and second logic signals.

14. A method of inverting a first logic signal and logically combining the first logic signal with a second logic signal, the method comprising the steps of:

providing an inverter having an input and an output;

providing a logic gate having first and second inputs, first and second power supply nodes, and an output for providing a logical NAND combination of the first and second logic signals;

coupling the first logic signal to the inverter input and the first input of the logic gate;

coupling the second logic signal to the second input of the logic gate;

coupling the first power supply node of the logic gate to the inverter output; and

coupling the second power supply node of the logic gate to a source of supply voltage.

15. A method of inverting a first logic signal and logically combining the first logic signal with a second logic signal, the method comprising the steps of:

providing an inverter having an input and an output;

providing a logic gate having first and second inputs, first and second power supply nodes, and an output for providing a logical NOR combination of the first and second logic signals;

coupling the first logic signal to the inverter input and the first input of the logic gate;

coupling the second logic signal to the second input of the logic gate;

coupling the first power supply node of the logic gate to the inverter output; and

coupling the second power supply node of the logic gate to a source of supply voltage.