Integrated circuit placement method using netlist and predetermined ordering constraints to produce a human readable integrated circuit schematic diagram

• US 5,187,784 A
• Filed: 01/13/1989
• Issued: 02/16/1993
• Est. Priority Date: 01/13/1989
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Rowson, James A.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Coleman, Eric
• Application Number:
  US07/297,353
• Time in Patent Office: 1,495 Days
• Field of Search: 395/500, 364/488, 364/489, 364/490, 364/491, 364/200 MS File, 364/900 MS File
• US Class Current: 716/122
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/18 Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling circuit design at the physical level G06F30/39; network planning tools for wireless communication networks H04W16/18
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method is disclosed for determining the placement of circuit elements in an integrated circuit where the circuit elements are initially represented by a netlist. The method preferably includes the steps of providing predetermined ordering constraints that indicate the preferred relative locations of the circuit elements that are represented in the netlist, partitioning the circuit elements from the netlist in accordance with a predetermined balancing criterion; determining the value of a cost function associated with the partitioning steps, and selecting a particular partition based upon the value of the cost function.

Claims

1. A computer-implemented method for placing circuit elements in an inegraded circuit schematic where the circuit elements are initially represented by a netlist to produce a human-readable schematic circuit layout from the netlist, comprising computer-implemented steps of:

(a) receiving predetermined ordering constraints indicating preferred relative vertical locations in a schematic diagram of circuit elements that are represented in the netlist;

(b) partitioning the circuit elements represented in the netlist in accordance with a predetermined balancing criterion;

(c) determining a first value of a cost function associated with the partitioning produced by the partitioning step, the determined value of he cost function being dependent upon he circuit elements crossing the partitioning and the predetermined ordering constraints in the cost function;

(d) repeating step (c) to obtain a second value of the cost function associated with a different partition;

(e) comparing the first and second values;

(f) selecting the partition having the lower cost value;

(g) assigning the circuit elements to two groups such that the one group is physically above the other group in the circuit schematic; and

(h) repeating steps (b) through (f) recursively to automatically produce horizontal subpartitions of the circuit elements represented by the netlist to produce a human readable schematic circuit layout.

2. The method of claim 1, wherein each ordering constraint has an associated cost penalty, said determining step assessing said cost penalty when a partition of said partitioning step leaves the ordering constraint unsatisfied.

3. The method of claim 1, wherein each ordering constraint provides an associated cost penalty to the value of he cost function.

4. The method of claim 3, wherein said ordering constraints relate to the horizontal locations of the circuit elements relative to one another, and said partitioning step produces vertical partitions.

5. The method of claim 4, further including a step of generating the predetermined ordering constraints to produce placement information for the circuit elements representing a predetermined directing of signal flow in the human readable schematic circuit layout.