Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache

• US 5,187,793 A
• Filed: 01/09/1989
• Issued: 02/16/1993
• Est. Priority Date: 01/09/1989
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Keith, John M., Sprague, David L., Goldstein, Judith A., Simon, Allen H., Dixon, Douglas F.
• Primary Examiner(s): Anderson, Lawrence E.
• Assistant Examiner(s): Coleman, Eric
• Application Number:
  US07/294,888
• Time in Patent Office: 1,499 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/375, 395/425, 395/775
• US Class Current: 712/225
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

An instruction caching system comprises meta-instructions which are contained within the program being executed. A meta-machine, which is a small segment of software, executes the meta-instructions and passes control to the processor itself at appropriate times to execute blocks of instructions from the instruction cache.

Claims

1. A hierarchical memory system for a digital data processor comprising:

(a) a relatively large, slow main memory;

(b) a relatively small, high speed cache memory;

(c) a plurality of meta-instructions, stored in said main memory, for controlling the loading and unloading of information in the cache memory, said plurality of meta-instructions comprising;

(i) a first meta-instruction for loading a block of machine instructions from said main memory into an instruction portion of said cache memory;

(ii) a second meta-instruction for causing the processor to execute a machine instruction at a specified location in the instruction portion of said cache memory; and

(iii) a third meta-instruction for executing a single machine instruction from said main memory;

(d) a meta-machine interpreter, comprising a machine instruction program stored in said cache memory, for executing said meta-instructions; and

(e) a special machine instruction for causing said meta-machine interpreter to execute a meta-machine at a specified location in said main memory.

2. A hierarchical memory system in accordance with claim 1 wherein said instruction portion of said cache memory includes a section for temporary storage of a meta-instruction when executed in a one-instruction-at-a-time mode.

3. A hierarchical memory system in accordance with claim 2 wherein said cache memory additionally comprises a data portion.

4. A hierarchical memory system in accordance with claim 3 wherein said data portion of said cache memory includes a meta-program counter section for storing a meta-program counter having a value which provides an address into said off-chip RAM.

5. A hierarchical memory system in accordance with claim 4 wherein the value of the meta-program counter is maintained by said meta-machine interpreter.

6. A hierarchical memory system in accordance with claim 5 wherein said cache memory includes a general-purpose section for use by executing programs.

7. A hierarchical memory system in accordance with claim 6 wherein said machine instruction comprises 48 bits.

8. A hierarchical memory system in accordance with claim 6 wherein said meta-instructions are each greater than 48 bits in length.

9. A hierarchical memory system in accordance with claim 6 wherein said instruction portion of said cache memory has a capacity of 256 instructions×

48-bits.

10. A hierarchical memory system in accordance with claim 6 wherein said data portion of said cache memory has a capacity of 256 words×

16 bits.

11. A hierarchical memory system for use in a digital data processor including a microprocessor formed on a semiconductor chip, said hierarchical memory system comprising:

(a) a relatively large, slow off-chip random access memory (RAM);

(b) a relatively small, high speed on-chip random access memory (RAM);

(c) a plurality of meta-instructions, stored in said main memory, for controlling the loading and unloading of information in the cache memory, said plurality of meta-instructions including;

(i) a first meta-instruction for loading a block of machine instructions from said off-chip RAM into an instruction portion of said on-chip RAM;

(ii) a second meta-instruction for causing the processor to execute a machine instruction at a specified location in the instruction portion of said on-chip RAM;

(iii) a third meta-machine instruction for executing a single machine instruction from said off-chip RAM;

(d) a meta-machine interpreter, comprising a machine instruction program located in said on-chip RAM, for executing the meta-instructions;

(e) a special machine instruction for causing the meta-machine interpreter to execute a meta-instruction at a specified location in said off-chip RAM; and

(f) a meta-program counter, residing in said on-chip RAM, said meta-program counter having a value, maintained by the meta-machine interpreter, which value provides an address into said off-chip RAM.