Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache
First Claim
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1. A hierarchical memory system for a digital data processor comprising:
- (a) a relatively large, slow main memory;
(b) a relatively small, high speed cache memory;
(c) a plurality of meta-instructions, stored in said main memory, for controlling the loading and unloading of information in the cache memory, said plurality of meta-instructions comprising;
(i) a first meta-instruction for loading a block of machine instructions from said main memory into an instruction portion of said cache memory;
(ii) a second meta-instruction for causing the processor to execute a machine instruction at a specified location in the instruction portion of said cache memory; and
(iii) a third meta-instruction for executing a single machine instruction from said main memory;
(d) a meta-machine interpreter, comprising a machine instruction program stored in said cache memory, for executing said meta-instructions; and
(e) a special machine instruction for causing said meta-machine interpreter to execute a meta-machine at a specified location in said main memory.
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Abstract
An instruction caching system comprises meta-instructions which are contained within the program being executed. A meta-machine, which is a small segment of software, executes the meta-instructions and passes control to the processor itself at appropriate times to execute blocks of instructions from the instruction cache.
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Citations
11 Claims
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1. A hierarchical memory system for a digital data processor comprising:
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(a) a relatively large, slow main memory; (b) a relatively small, high speed cache memory; (c) a plurality of meta-instructions, stored in said main memory, for controlling the loading and unloading of information in the cache memory, said plurality of meta-instructions comprising; (i) a first meta-instruction for loading a block of machine instructions from said main memory into an instruction portion of said cache memory; (ii) a second meta-instruction for causing the processor to execute a machine instruction at a specified location in the instruction portion of said cache memory; and (iii) a third meta-instruction for executing a single machine instruction from said main memory; (d) a meta-machine interpreter, comprising a machine instruction program stored in said cache memory, for executing said meta-instructions; and (e) a special machine instruction for causing said meta-machine interpreter to execute a meta-machine at a specified location in said main memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A hierarchical memory system for use in a digital data processor including a microprocessor formed on a semiconductor chip, said hierarchical memory system comprising:
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(a) a relatively large, slow off-chip random access memory (RAM); (b) a relatively small, high speed on-chip random access memory (RAM); (c) a plurality of meta-instructions, stored in said main memory, for controlling the loading and unloading of information in the cache memory, said plurality of meta-instructions including; (i) a first meta-instruction for loading a block of machine instructions from said off-chip RAM into an instruction portion of said on-chip RAM; (ii) a second meta-instruction for causing the processor to execute a machine instruction at a specified location in the instruction portion of said on-chip RAM; (iii) a third meta-machine instruction for executing a single machine instruction from said off-chip RAM; (d) a meta-machine interpreter, comprising a machine instruction program located in said on-chip RAM, for executing the meta-instructions; (e) a special machine instruction for causing the meta-machine interpreter to execute a meta-instruction at a specified location in said off-chip RAM; and (f) a meta-program counter, residing in said on-chip RAM, said meta-program counter having a value, maintained by the meta-machine interpreter, which value provides an address into said off-chip RAM.
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Specification