Method of manufacturing SOI semiconductor element

• US 5,188,973 A
• Filed: 04/30/1992
• Issued: 02/23/1993
• Est. Priority Date: 05/09/1991
• Status: Expired due to Term

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone Corporation
• Inventors: Kunii, Yasuo, Izumi, Katsutoshi, Omura, Yasuhisa
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/877,446
• Time in Patent Office: 299 Days
• Field of Search: 437/21, 437/40, 437/41, 437/61, 437/89, 437/90, 437/203, 357/23.7, 148/DIG. 152
• US Class Current: 438/157
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

According to a method of manufacturing an SOI semiconductor element of this invention, a structure obtained by forming a first semiconductor layer on a first insulator is prepared. A process mask is arranged on the first semiconductor layer. The process mask has a groove pattern of a predetermined size. A groove extending between the first semiconductor layer and the first insulator layer is formed by etching the first semiconductor layer on the basis of the groove pattern of the process mask to expose the first insulator layer and etching the first insulator layer to a predetermined depth. A second semiconductor layer serving as a buried electrode is formed in the groove such that a level of an upper surface of the second semiconductor layer is equal to a level of a bottom surface of the first semiconductor layer. A second insulator layer is formed on the second semiconductor layer. Crystalline growth of a semiconductor layer is performed from side surfaces of the groove to bury the groove with a monocrystalline semiconductor. A source region and a drain region are formed in the monocrystalline semiconductor buried in the groove. A gate electrode is formed on the monocrystalline semiconductor through a gate oxide film.

Claims

1. A method of manufacturing an SOI semiconductor element, comprising the steps of:

preparing a structure obtained by forming a first semiconductor layer on a first insulator;

arranging a process mask on said first semiconductor layer, said process mask having a groove pattern of a predetermined size;

forming a groove extending between said first semiconductor layer and said first insulator layer by etching said first semiconductor layer on the basis of the groove pattern of said process mask to expose said first insulator layer and etching said first insulator layer to a predetermined depth;

forming a second semiconductor layer serving as a buried electrode in said groove such that a level of an upper surface of said second semiconductor layer is equal to a level of a bottom surface of said first semiconductor layer;

forming a second insulator layer on said second semiconductor layer;

performing crystalline growth of a semiconductor layer from side surfaces of said groove to bury the groove with a monocrystalline semiconductor;

forming a source region and a drain region in said monocrystalline semiconductor buried in said groove; and

forming a gate electrode on said monocrystalline semiconductor through a gate oxide film.

2. A method according to claim 1, wherein the step of preparing said structure comprises the step of burying an oxide layer in a semiconductor substrate to form said first insulator layer and said first semiconductor layer on said semiconductor substrate.

3. A method according to claim 1, wherein the step of preparing said structure comprises the step of forming a monocrystalline semiconductor layer on an oxide layer to form said first insulator layer and said semiconductor layer.

4. A method according to claim 1, wherein the step of preparing said structure comprises the step of forming a monocrystalline semiconductor layer on an oxide layer to form said first insulator layer and said first semiconductor layer.

5. A method according to claim 1, wherein the step of preparing said structure comprises the step of oxidizing one surface of a monocrystalline semiconductor layer to form said first insulator, while the rest of said monocrystalline semiconductor layer is used as said first semiconductor layer.

6. A method according to claim 1, wherein said first insulator layer is a silicon oxide film, and said first semiconductor layer is a silicon layer.

7. A method according to claim 6, further comprising:

the step of sequentially forming a silicon oxide film layer and a silicon nitride film layer on said first semiconductor layer of said structure before the step of arranging said process mask; and

after the step of forming said groove,

the step of removing said process mask,

the step of oxidizing a side wall of said first semiconductor layer exposed in said groove, and

the step of forming a silicon nitride film in said groove.

8. A method of according to claim 7, wherein the step of forming said semiconductor layer as said buried electrode comprises the steps of:

forming a second semiconductor layer consisting of a silicon semiconductor on a silicon nitride film including said groove; and

etching said second semiconductor layer such that a level of an upper surface of said second semiconductor layer in said groove is set to be equal to a level of a lower surface of said first semiconductor layer.

9. A method according to claim 8, further comprising the steps of:

removing said silicon nitride film exposed in said groove to expose an oxide film;

removing said oxide film in said groove to expose said first semiconductor layer;

forming a silicon nitride film in said groove; and

removing said silicon nitride film from an upper surface of said second semiconductor layer to expose said second semiconductor layer;

wherein said second insulator layer is formed on said exposed second semiconductor layer.

10. A method according to claim 9, wherein the step of performing crystalline growth of a semiconductor layer from side surfaces of said groove to bury the groove with a monocrystalline semiconductor comprises the step of crystallizing said first semiconductor layer into a monocrystalline semiconductor layer.