High density circuit board and method of making same

• US 5,191,174 A
• Filed: 08/01/1990
• Issued: 03/02/1993
• Est. Priority Date: 08/01/1990
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Snyder, Keith A., Wiley, John P., Hoffarth, Joseph G., Markovich, Voya R., Chang, Chi S.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): Korka, Trinidad
• Application Number:
  US07/561,401
• Time in Patent Office: 944 Days
• Field of Search: 174/266, 174/250, 174/262, 174/255, 29/830, 29/831, 361/414, 361/412, 361/410, 361/416
• US Class Current: 174/266
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/0352 Differences between the conductors of different layers of a multilayer
• CPC Class Codes: H05K 2201/09518 Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/09845 Stepped hole, via, edge, bump or conductor
• CPC Class Codes: H05K 2203/061 of previously made multilayered subassemblies laminating only or mainly similar single-sided circuit boards H05K3/4617; laminating only or mainly similar double-sided circuit boards H05K3/462
• CPC Class Codes: H05K 3/0032 of organic insulating material
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/4614 the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: H05K 3/462 characterized by laminating only or mainly similar double-sided circuit boards
• CPC Class Codes: H05K 3/4623 the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: Y10T 29/49126 Assembling bases

Abstract

A multilayered circuit board assembly which includes a plurality of layered subassemblies each having electrically conducting wiring and at least one through hole therein. A first of these subassemblies possesses a greater wiring dnesity than the others while a second subassembly possesses a lesser resistance (and wiring density) than the others. In one example, several (e.g. at least four) such layered subassemblies may be included in the overall assembly such that those layers located along one side of the board may possess substantially greater wiring densities than the layers on the other side of the board while those layers on said other side will in turn possess lesser resistance (and greater current capacities). There are also described at least three methods for making the above multilayered circuit board assembly. Such a structure may be utilized in supercomputer applications.

Claims

1. In a multilayered circuit board assembly including first, second and third layered subassemblies arranged in a serially contiguous manner, each of said subassemblies having at least one dielectric layer, electrically conducting wiring in the form of at least one conductive layer and at least one through hole therein, each of said subassemblies further including a predetermined wiring density and an electrical current resistance, the improvement wherein said wiring densities and said electrical current resistances of said subassemblies progressively decrease from said first subassembly to said third subassembly.

2. The improvement according to claim 1 further including a fourth layered subassembly located adjacent and contiguous to said third layered subassembly and possessing a wiring density and an electrical current resistance progressively less than said wiring density and said electrical current resistance of said third layered subassembly.

3. The improvement according to claim 1 wherein each of said layered subassemblies include a plurality of through holes therein, at least some of said through holes being in alignment.

4. The improvement according to claim 3 wherein at least some of said aligning through holes in said layered subassemblies are substantially similar in size.

5. The improvement according to claim 4 wherein said aligning through holes include a continuous conductive layer therein.

6. The improvement according to claim 3 wherein at least some of said aligning through holes in said layered subassemblies are progressively larger from said first layered subassembly to said third layered subassembly.

7. The improvement according to claim 6 wherein said aligning through holes of progressively larger size include a continuous conductive layer therein.

8. The improvement according to claim 7 further including a dielectric layer interconnecting said layered subassemblies and substantially surrounding the locations of intersection between said aligning through holes and said continuous conductive layers therein.

9. The improvement according to claim 3 wherein said aligning through holes each include an extending conductive end segment at the end of said through hole that aligns with a respective other through hole, said extending conductive end segments of each of said through holes being electrically connected.

10. The improvement according to claim 9 further including a common layer of conductive material located between and in contact with each of said aligned and electrically connected conductive end segments.

11. The improvement according to claim 10 wherein each of said conductive end segments is comprised of copper and said common layer of conductive material is comprised of tin.

12. The improvement according to claim 1 wherein the current capacities of said layered subassemblies increases from said first layered subassembly to said third layered subassembly.

13. The improvement according to claim 1 wherein the spacing of said conducting wiring of said layered subassemblies increases from said first layered subassembly to said third layered subassembly.

14. The improvement according to claim 1 wherein the thickness of said conducting wiring of said layered subassemblies increases from said first layered subassembly to said third layered subassembly.

15. The improvement according to claim 1 wherein the number of through holes in said layered subassemblies progressively decreases from said first layered subassembly to said third layered subassembly.

16. A method of making a multilayered circuit board assembly including at least three layered subassemblies, each of said layered subassemblies having at least one dielectric layer, electrically conducting wiring in the form of at least one conductive layer and at least one through hole therein, each of said layered subassemblies including a predetermined wiring density and electrical current resistance, said method comprising the steps of:

aligning said three layered subassemblies in a serially contiguous manner;

providing at least one common through hole through said first, second and third layered subassemblies;

providing a layer of conductive material within said common through hole and extending through said first, second and third layered subassemblies; and

bonding said three layered subassemblies together to form said multilayered circuit board assembly, said wiring densities and said electrical current resistances of said layered subassemblies progressively decreasing from said first layered subassembly to said third layered subassembly.

17. The method according to claim 16 further including aligning a fourth layered subassembly in contiguous manner with said third layered subassembly, extending said common through hole and said layer of conductive material within said common through hole through said fourth layered subassembly, and bonding said fourth layered subassembly to said third layered subassembly, said wiring density and said electrical current resistance of said fourth layered subassembly being progressively less than said wiring density and said electrical current resistance of said third layered subassembly.

18. A method of making a multilayered circuit board assembly including at least three layered subassemblies, each of said layered subassemblies having at least one dielectric layer, electrically conducting wiring in the form of at least one conductive layer and at least one through hole therein, each of said layered subassemblies including a predetermined wiring density and electrical current resistance, said method comprising the steps of:

providing at least one through hole in each of said layered subassemblies;

aligning said layered subassemblies having said though holes therein relative to one another such that said layered subassemblies are arranged in a serially contiguous manner and at least some of said through holes are aligned with one another;

bonding said aligned layered subassemblies having said aligned through holes to form a multilayered structure; and

providing a continuous conductive layer within each of said aligned through holes, said wiring densities and said electrical current resistances of said layered subassemblies progressively decreasing from said first layered subassembly to said third layered subassembly.

19. The method according to claim 18 further including the step of providing a quantity of dielectric adhesive material between said layered subassemblies prior to said bonding thereof.

20. The method according to claim 19 further including the step of removing selected quantities of said dielectric adhesive material from between said layered subassemblies subsequent to said bonding, said selected quantities being removed located substantially within said aligned through holes.

21. The method according to claim 20 wherein said removal of said dielectric adhesive material is achieved using laser ablation.