Integrated circuit structure analysis

• US 5,191,213 A
• Filed: 07/05/1991
• Issued: 03/02/1993
• Est. Priority Date: 07/05/1990
• Status: Expired due to Term

• Current Assignee: Olivetti Systems & Networks SRL
• Original Assignee: Olivetti Systems & Networks SRL
• Inventors: Blythe, Simon, Fraboni, Beatrice, Ahmed, Haroon
• Primary Examiner(s): Anderson, Bruce C.
• Application Number:
  US07/725,303
• Time in Patent Office: 606 Days
• Field of Search: 250/310, 250/307, 250/397
• US Class Current: 250/310
• CPC Class Codes: G01R 31/305 using electron beams investigating or analysing materials by measuring photoelectric effect G01N23/227
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01J 2237/2441 Semiconductor detectors, e.g. diodes
• CPC Class Codes: H01J 2237/2443 Scintillation detectors
• CPC Class Codes: H01J 2237/24465 Sectored detectors, e.g. quadrants
• CPC Class Codes: H01J 2237/24475 Scattered electron detectors
• CPC Class Codes: H01J 2237/2448 Secondary particle detectors
• CPC Class Codes: H01J 2237/24507 Intensity, dose or other characteristics of particle beams or electromagnetic radiation
• CPC Class Codes: H01J 2237/24592 Inspection and quality control of devices
• CPC Class Codes: H01J 37/244 Detectors; Associated components or circuits therefor

Abstract

The structure of a multilayered integrated circuit is determined by removing successive layers of the circuit. Following removal of each layer, the revealed surface is scanned by an electron beam. The intensity of backscattered or secondary electrons is detected by a first or second detector respectively. From the detected electron intensities, image processing circuitry derives a representation of the integrated circuit surface scanned. Where the surface of the integrated circuit is a flat layer of semiconductor substrate material having implanted doped areas, the surface is covered with a metallisation layer providing a Schottky barrier junction with the doped areas. Electron beam scanning of the metallisation layer induces a current at this junction which is monitored and processed to derive a representation of the outline of the doped implanted areas.

Claims

1. Apparatus for determining the structure of an integrated circuit of the type comprising different layers, including metallic and non-metallic features, and a body including at least one region with a higher type-p or type-n dopant concentration with respect to adjacent regions, said apparatus comprising:

an electron beam source;

means for focussing an electron beam from said source and for controllably scanning said electron beam over a surface of said integrated circuit;

a first detector responsive to backscattered electrons from the surface of said integrated circuit to represent said metallic features;

a second detector responsive to secondary electrons emitted by said surface to represent said non-metallic features; and

processing means coupled to each of said first and second detectors and operable to derive a representation of said metallic and non-metallic features of said layers from signals from said first and second detectors;

the improvement comprising means for representing said one region with the higher type-p or type-n dopant concentration as induced at a Schottky barrier junction in said one region, said means comprising;

a third detector connected with a metallisation layer of one of a first type of metal or a second type of metal to define the Schottky barrier junction with said region with respecitve ones of the higher type-p dopant concentration or type-n dopant concentration, and

current sensing means connected with said third detector for sensing a current arising from said Schottky barrier junction as said electron beam scans said metallisation layer; and

wherein said processing means are also coupled to said third detector and are operable to derive a representation of said at least one region with the higher type-p doped or type-n doped concentration from signals from said third detector.

2. The invention set forth in claim 1, wherein said first detector is a thin p-n junction diode.

3. The invention set forth in claim 1, wherein said first detector is an annular assembly comprising four quadrants, each of said quadrants being a separate p-n junction diode, said first detector being positioned such that said focussed electron beam passes through said aperture therein.

4. The invention set forth in claim 1, including means for controllably moving said integrated circuit relative to said electron beam source.

5. The invention set forth in claim 4, wherein said means for controllably moving said integrated circuit comprise a pair of stepper motor and lead screw assemblies arranged to move said integrated circuit in either of two mutually perpendicular directions in a plane perpendicular to said electron beam from said electron beam source.

6. The invention set forth in claim 1, including means for removing selected features from a layer of said integrated circuit.

7. The invention set forth in claim 6, wherein said means for removing selected features comprise a source of gas plasma and means for applying said gas plasma to said selected feature.

8. The invention set forth in claim 1, wherein said metallisation layer is of a material sealected from the group comprising gold, aluminium, titanium, and paladium.

9. The invention set forth in claim 1, including means operable to display at least one said derived representation.

10. The apparatus set forth in claim 1 for representing features of an integrated circuit, wherein said first type of metal is gold and wherein said one region includes a higher concentration of p-type dopant.

11. The apparatus set forth in claim 1 for representing features of an integrated circuit, wherein said first type of metal is aluminum and wherein said one region includes a higher concentration of n-type dopant.

12. The apparatus set forth in claim 1 for representing features of an integrated circuit wherein said metallisation layer has a minimum thickness of 20 nanometers.

13. A method of determining the structure of an integrated circuit, including the steps of:

a) scanning a surface of said integrated circuit with an electron beam;

b) detecting electrons, said electrons being selected from the group comprising backscattered electrons from said scanned surface and secondary electrons emitted by said scanned surface;

c) deriving a representation of said scanned surface from said detected electrons;

d) removing a layer of predetermined thickness from said scanned surface;

e) repeating steps a) to c) at least once; and

f) storing at least a part of each said derived representation.

14. The invention set forth in claim 13, wherein said stored part of a derived representation for a first layer includes a reference portion, and wherein said reference portion locates said derived representation for said first layer with respect to a derived representation for a next layer.

15. The invention set forth in claim 14, wherein said reference portion comprises at least one selected feature of said first layer which also occurs at the same position in said next layer.

16. The invention set forth in claim 14, wherein said reference portion comprises at least one selected feature of said next layer which may be detected prior to removal of said first layer.

17. The invention set forth in claim 13, wherein, when said integrated circuit includes a passivation layer of silicon dioxide or silicon nitrate, said passivation layer is removed by dry etching with a mixture of carbon tetrafluoride and oxygen.

18. The invention set forth in claim 13, wherein removal of aluminium layers of or aluminium features of layers is achieved by dry etching with silicon tetrachloride.

19. The invention set forth in claim 18, wherein, following said etching by silicon tetrachloride, a mixture of carbon tetrafluoride and oxygen is applied to passivate the aluminium.

20. The invention set forth in claim 19, wherein said mixture is 90% carbon tetrafluoride and 10% oxygen.

21. The invention set forth in claim 13, wherein removal of polysilicon layers or features of layers is achieved by etching beneath them with hydrofluoric acid.

22. The invention set forth in claim 13, wherein removal of gold layers or gold features of layers is achieved by inert gas bombardment.

23. The invention set forth in claim 22, wherein said inert gas is argon.

24. The invention set forth in claim 13, wherein said step of scanning said surface with a focussed electron beam comprises dividing said surface into separate areas and raster scanning successive ones of said separate areas.

25. The invention set forth in claim 13, including the step of image processing of said derived representation wherein the intensity of said detected electrons for each point on said scanned surface is compared with a threshold value and each such point is assigned a first or second value in dependence on whether said intensity is greater or less than said threshold value.

26. The invention set forth in claim 25, including the step of displaying said derived representation wherein said displayed points are black or white depending on whether they have been assigned said first or second value.

27. The invention set forth in claim 13, wherein, when there are surface features of interest which are metal, said representation is derived from said detected backscattered electrons.

28. The invention set forth in claim 13, wherein, when there are surface features of interest which are non-metallic, said representation is derived from said detected secondary electrons.

29. The invention set forth in claim 13, including the step of reducing the power of said focussed electron beam when said scanned surface is non-metallic.

30. A method for removing selected features from a layer of an integrated circuit comprising the steps of:

scanning a surface of said layer with an electron beam;

detecting electrons, said electrons being selected from the group comprising backscattered electrons from said scanned surface and secondary electrons emitted by said scanned surface;

deriving a representation of said selected features of said scanned surface from said detected electrons;

storing said derived representation;

covering said surface with a layer of etch resistant material;

developing said layer of etch resistant material with said selected features of the scanned surface from said derived and stored representation;

removing said etch resistant material covering said selected features of said scanned surface; and

etching away said selected features of said scanned surface.

31. The invention set forth in claim 30, wherein, when said integrated circuit includes a passivation layer of silicon dioxide or silicon nitrate, said passivation layer is removed by dry etching with a mixture of carbon tetrafluoride and oxygen.

32. The invention set forth in claim 30, wherein removal of aluminium layers of or aluminium features of layers is achieved by dry etching with silicon tetrachloride.

33. The invention set forth in claim 32, wherein, following said etching by silicon tetrachloride, a mixture of carbon tetrafluoride and oxygen is applied to passivate the aluminium.

34. The invention set forth in claim 33, wherein said mixture is 90% carbon tetrafluoride and 10% oxygen.

35. The invention set forth in claim 30, wherein removal of polysilicon layers or features of layers is achieved by etching beneath them with hydrofluoric acid.

36. The invention set forth in claim 30, wherein removal of gold layers or gold features of layers is achieved by inert gas bombardment.

37. The invention set forth in claim 36, wherein said inert gas is argon.

38. The invention set forth in claim 30, wherein said step of scanning said surface with a focussed electron beam comprises dividing said surface into separate areas and raster scanning successive ones of said separate areas.

39. The invention set forth in claim 30, including the step of image processing of said derived representation wherein the intensity of said detected electrons for each point on said scanned surface is compared with a threshold value and each such point is assigned a first or second value in dependence on whether said intensity is greater or less than said threshold value.

40. The invention set forth in claim 39, including the step of displaying said derived representation wherein said displayed points are black or white depending on whether they have been assigned said first or said second value.

41. The invention set forth in claim 30, wherein, when there are surface features of interest which are metal, said representation is derived from said detected backscattered electrons.

42. The invention set forth in claim 30, wherein, when there are surface features of interest which are non-metallic, said representation is derived from said detected secondary electrons.

43. The invention set forth in claim 30, including the step of reducing the power of said focussed electron beam when said scanned surface is non-metallic.

44. A method of determining the location, in a surface of a body of semiconductor material, of first and second regions of said body having higher dopant concentration of type-p dopant and type-n dopant, respectively, with respect to contiguous portions of said body, said method comprising the steps of:

depositing a metallisation layer of a first type on said surface so as to form a first Schottky barrier junction with one of the first and second regions of said body;

controllably scanning said metallisation layer of a first type with a focussed electron beam;

sensing the current arising from said first Schottky barrier junction as said beam scans said metallisation layer to represent said one of the first and second regions in said surface;

removing said metallisation layer of a first type and replacing it with a metallisation layer of a second type so as to form a second Schottky barrier junction with another of the first and second regions of said body;

controllably scanning said metallisation layer of a second type with a focussed electron beam;

sensing the current arising from said second Schottky barrier junction as said beam scans said metallisation layer of a second type to represent said other of the first and the second regions in said surface; and

providing a derived representation of said surface in response to the current arising from said first and second Schottky barriers.

45. The invention set forth in claim 44 including the steps of attaching an electrical contact to each of said metallisation layer and said body.

46. The invention set forth in claim 45 including the step of electrically connecting said body to ground potential.

47. The invention set forth in claim 45 wherein attachment of said electrical contact to said metallisation layer is achieved by locating said contact adjacent said body such that, when said metallisation layer is deposited on said surface, said metallisation layer extends to connect with said contact.

48. The invention set forth in claim 45 wherein said electrical contact to said metallisation layer is a wire, an end of said wire being connected to a surface of said metallisation layer.

49. The invention set forth in claim 44, wherein the material of said metallisation layer is selected from the group comprising gold, aluminium, titanium, and paladium.

50. The invention set forth in claim 44, wherein the depth of said deposited metallisation layer is at least 20 nm.

51. The invention set forth in claim 44, including the step of removing said metallisation layer with a mixture of concentrated nitric and hydrochloric acids.

52. The invention set forth in claim 44, wherein, when said integrated circuit includes a passivation layer of silicon dioxide or silicon nitrate, said passivation layer is removed by dry etching with a mixture of carbon tetrafluoride and oxygen.

53. The invention set forth in claim 44, wherein removal of aluminium layers of or aluminium features of layers is achieved by dry etching with silicon tetrachloride.

54. The invention set forth in claim 53 wherein, following said etching by silicon tetrachloride, a mixture of carbon tetrafluoride and oxygen is applied to passivate the aluminium.

55. The invention set forth in claim 54 wherein said mixture is 90% carbon tetrafluoride and 10% oxygen.

56. the invention set forth in claim 44 wherein removal of polysilicon layers or features of layers is achieved by etching beneath them with hydrofluoric acid.

57. The invention set forth in claim 44 wherein removal of gold layers or gold features of layers is achieved by inert gas bombardment.

58. The invention set forth in claim 57 wherein said inert gas is argon.

59. The invention set forth in claim 44, wherein said step of scanning said surface with a focussed electron beam comprises dividing said surface into separate areas and raster scanning successive ones of said separate areas.

60. The invention set forth in claim 44, including the step of image processing of said derived representation wherein the intensity of said detected electrons for each point on said scanned surface is compared with a threshold value and each such point is assigned a first or second value in dependence on whether said intensity is greater or less than said threshold value.

61. The invention set forth in claim 60, including the step of displaying said derived representation wherein said displayed points are black or white depending on whether they have been assigned said first or said second value.

62. The method set forth in claim 44, wherein said metallisation layer of a first type is gold and wherein said one of the first and second regions of said body includes a higher concentration of p-type dopant.

63. The method set forth in claim 44, wherein said metallisation layer of a second type is aluminum and wherein said other of the first and second regions of said body includes a higher concentration of p-type dopant.

64. The apparatus set forth in claim 44 for representing features of an integrated circuit wherein said metallisation layer has a minimum thickness of 20 nanometers.