Phase shift vernier for automatic test systems
First Claim
1. A phase shift vernier for an automatic test system for testing integrated circuit devices, said phase shift vernier providing an output signal from an integrated circuit device with continuously variable delay based on an input phase delay value, comprising:
- delay value means for receiving said input phase delay value, said input phase delay value indicating an amount of delay for said output signal from said integrated circuit device;
ring oscillator means for circulating an oscillating signal through a plurality of differential stages to generate a plurality of pairs of quadrature signals with a plurality of phase delays, said oscillating signal having a predetermined frequency, each of said differential stages being connected in series, each of said stages phase-shifting its inputs by a predetermined phase delay to generate its differential outputs from each stage;
multiplexor means coupled to said ring oscillator means and to said delay value means for receiving said plurality of pairs of quadrature signals from said ring oscillator means, said multiplexor means selecting first and second signals from said plurality of pairs of quadrature signals from said ring oscillator means in response to said input phase delay value from said delay value means;
DAC means coupled to said multiplexor means and to said delay value means for generating first and second currents, said DAC means generating a current amplitude ("M") based on a predetermined number of least significant bits of said input phase delay value from said delay value means, said first and second currents having an amplitude ratio of (1-0.2*M)/M;
combiner means coupled to said DAC means and to said multiplexor means for generating said output signal whose phase is said first quadrature signal shifted by said input phase delay value, said combiner means multiplying said first and second quadrature signals with said first and second currents to generate third and fourth quadrature signals, respectively, said third and fourth quadrature signals having amplitudes equal to the amplitudes of said first and second currents, respectively, said combiner means further adding said third and fourth quadrature signals to generate said output signal shifted by said input phase delay value.
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Abstract
A phase shift vernier for providing an output signal with continuously variable delay based on an input phase delay is disclosed. The apparatus comprises delay value means, a ring oscillator, a multiplexer, a DAC, and a signal combiner. The delay value means is adapted for receiving an input phase delay value, indicating the amount of delay for an output signal. The ring oscillator is adapted for circulating an oscillating signal through multiple differential stages to generate multiple quadrature signals. The oscillating signal has a predetermined frequency and each of the differential stages is connected in series. Each of the stages delays its inputs by a predetermined amount to generate its differential outputs from each stage. The multiplexor is coupled to the ring oscillator and to the delay value means to receive the quadrature signals from the ring oscillator. The multiplexor selects first and second quadrature signals from the ring oscillator in response to the input phase delay from the delay value means. The first and second quadrature signals are offset by 90 degrees. The DAC is coupled to the multiplexor and to the delay value means to generate a first and second currents based on the input phase delay from the delay value means. The signal combined is coupled to the DAC and to the multiplexor for generating the output signal phase-shifted by the input phase delay. The signal combiner multiplies the first and second quadrature signals with the first and second currents to generate third and fourth quadrature signals, respectively. The signal combiner further combines the third and fourth quadrature signals to generate the output signal.
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Citations
11 Claims
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1. A phase shift vernier for an automatic test system for testing integrated circuit devices, said phase shift vernier providing an output signal from an integrated circuit device with continuously variable delay based on an input phase delay value, comprising:
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delay value means for receiving said input phase delay value, said input phase delay value indicating an amount of delay for said output signal from said integrated circuit device; ring oscillator means for circulating an oscillating signal through a plurality of differential stages to generate a plurality of pairs of quadrature signals with a plurality of phase delays, said oscillating signal having a predetermined frequency, each of said differential stages being connected in series, each of said stages phase-shifting its inputs by a predetermined phase delay to generate its differential outputs from each stage; multiplexor means coupled to said ring oscillator means and to said delay value means for receiving said plurality of pairs of quadrature signals from said ring oscillator means, said multiplexor means selecting first and second signals from said plurality of pairs of quadrature signals from said ring oscillator means in response to said input phase delay value from said delay value means; DAC means coupled to said multiplexor means and to said delay value means for generating first and second currents, said DAC means generating a current amplitude ("M") based on a predetermined number of least significant bits of said input phase delay value from said delay value means, said first and second currents having an amplitude ratio of (1-0.2*M)/M; combiner means coupled to said DAC means and to said multiplexor means for generating said output signal whose phase is said first quadrature signal shifted by said input phase delay value, said combiner means multiplying said first and second quadrature signals with said first and second currents to generate third and fourth quadrature signals, respectively, said third and fourth quadrature signals having amplitudes equal to the amplitudes of said first and second currents, respectively, said combiner means further adding said third and fourth quadrature signals to generate said output signal shifted by said input phase delay value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification