Wideband transmission-mode FET linearizer

• US 5,191,338 A
• Filed: 11/29/1991
• Issued: 03/02/1993
• Est. Priority Date: 11/29/1991
• Status: Expired due to Term

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: General Electric Company
• Inventors: Katz, Allen, Moochalla, Shabbir S.
• Primary Examiner(s): Issing, Gregory C.
• Application Number:
  US07/800,375
• Time in Patent Office: 459 Days
• Field of Search: 330/107, 330/110, 330/277, 330/286, 330/280, 330/284, 330/304, 333/81 R, 333/18, 333/28 R, 333/164, 307/501, 342/352, 342/353
• US Class Current: 342/352
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/72 the amplifier stage being a common gate configuration MOSFET
• CPC Class Codes: H03F 3/601 using FET's, e.g. GaAs FET's H03F3/607, H03F3/608 take precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence

Abstract

A FET is operated without source-to-drain bias, with the source-to-drain conductive path coupled in series with a transmission line. A gate-to-ground impedance is selected in conjunction with a gate voltage near pinchoff to impress nonlinear distortion or gain and/or phase of signals traversing the source-to-drain conductive path. The nonlinear distortion can compensate for the amplitude distortion of a following amplifier, but the phase distortion may not be suitable for correcting that of the following amplifier. An inductor is bridged from source to drain, and corrects the phase without excessive effect on the amplitude. The magnitude of the inductor may be adjusted to minimize nonlinear amplitude change without affecting the phase change, whereupon the phase change may be made independent of amplitude change. A resistor in series with the bridging inductor can be selected to render amplitude change independent of phase change. Two such independent amplitude and phase correctors may be cascaded.

Claims

1. A circuit for, within a particular frequency range, distorting at least one of (a) amplitude and (b) phase of signal to be distorted, in response to the amplitude of said signal to be distorted, said circuit comprising:

a FET including a gate electrode, and also including source and drain electrodes and a controllable path for the flow of signal therebetween;

bias means coupled to said gate electrode and to at least one of said source and drain electrodes, for applying bias voltage to said gate electrode for controlling said FET for distortion of signals traversing said controllable path;

reactance means coupled between said gate electrode and a point of reference potential, said reactance means being selected to have a range of values, within said frequency range, for coacting with said bias for controlling said FET for distortion of said signals traversing said controllable path;

inductance means including first and second ends;

first coupling means coupled to said inductance means and to said FET, for coupling said first end of said inductance means to said source and said second end to said drain, for providing a path for flow of said signal parallel to said controllable path; and

second coupling means for coupling said signal to be distorted to one of said source and drain electrodes, for causing said signal to traverse said controllable path at least once, and for coupling the resulting distorted signal to utilization means.

2. A circuit according to claim 1, wherein said first coupling means comprises low resistance galvanic connections, whereby said inductance means is coupled to said source and drain electrodes by low impedances, and said source and drain electrodes are, at zero frequency, constrained to be at the same direct potential.

3. A circuit according to claim 1 wherein said second coupling means couples said signal to be distorted to said source electrode, and couples said drain electrode to said utilization means.

4. A circuit according to claim 1, wherein said inductance means includes a capacitor in parallel with an inductor, for generating a circuit parallel-resonant at a frequency, whereby the impedance of said parallel-resonant circuit is inductive below said frequency.

5. A circuit according to claim 1, wherein said first coupling means comprises resistance means.

6. A circuit according to claim 5 wherein the value of said resistance means is selected to minimize changes of phase shift in response to the power level of signals traversing said circuit.

7. A circuit for, within a particular frequency range, distorting at least one of (a) amplitude and (b) phase of signal to be distorted, in response to the amplitude of said signal to be distorted, said circuit comprising:

a FET including a gate electrode, and also including source and drain electrodes and a controllable path for the flow of signal therebetween;

bias means coupled to said gate electrode and to at least one of said source and drain electrodes, for applying bias voltage to said gate electrode for controlling said FET for distortion of signals traversing said controllable path;

reactance means coupled between said gate electrode and a point of reference potential, said reactance means being selected to have a range of values, within said frequency range, for coacting with said bias for controlling said FET for distortion of said signals traversing said controllable path;

impedance means including first and second ends, said impedance means having said first end coupled to said source electrode and said second end coupled to said drain electrode, for providing an alternate path for the flow of said signal between said source electrode and said drain electrode; and

coupling means coupled to said signal to be distorted to one of said source electrode and said drain electrode, for causing said signal to traverse said controllable path and said alternate path to thereby generate distorted signal, and for coupling said distorted signal to utilization means.

8. A circuit according to claim 7, wherein said impedance means comprises inductance means.

9. A circuit according to claim 7, wherein said impedance means is linear.

10. A circuit according to claim 8, wherein said inductance means includes a capacitor in parallel with an inductor.

11. A circuit according to claim 7, wherein said impedance means comprises inductance means serially coupled with resistance means.

12. A circuit according to claim 11, wherein said resistance means has a value selected to minimize changes in phase shift in response to the power level of signals traversing said circuit.

13. A satellite, comprising:

a body;

antenna means mounted to said body for receiving signals to produce received signals, and for transmitting signals to be transmitted;

signal processing and multiplexing means coupled to said antenna means for dividing said received signals to produce separate signals in a first plurality of independent channels;

a second plurality of amplifier means;

switch means coupled to said signal processing and multiplexing means for associating one of said amplifier means with each of said channels for producing amplified signals;

signal combining means coupled to said switch means for demultiplexing said amplified signals to produce a combined signal to be transmitted, and coupled to said antenna means for causing said combined signal to be transmitted; and

a plurality of distortion linearizers, each associated with one of said amplifier means, each of said distortion linearizers being, in at least one position of said switch means, coupled for linearizing signals in one of said channels, each of said distortion linearizers including;

(a) a FET including a gate electrode, and also including source and drain electrodes and a controllable path for the flow of signal therebetween;

(b) bias means coupled to said gate electrode and to at least one of said source and drain electrodes, for applying bias voltage to said gate electrode for controlling said FET for distortion of signals traversing said controllable path;

(c) reactance means coupled between said gate electrode and a point of reference potential, said reactance means being selected to have a range of values, within said frequency range, for coacting with said bias for controlling said FET for distortion of said signals traversing said controllable path;

(d) inductance means including first and second ends;

(e) first coupling means coupled to said inductance means and to said FET, for coupling said first end of said inductance means to said source and said second end to said drain, for providing a path for flow of said signal parallel to said controllable path; and

(f) second coupling means for coupling said signal to be distorted to one of said source and drain electrodes, for causing said signal to traverse said controllable path at least once, and for coupling the resulting distorted signal to utilization means.

14. A satellite according to claim 13, wherein said first plurality is less than said second plurality.

15. A satellite according to claim 13, wherein each of said distortion linearizers is coupled in its own channel between (A) said signal processing and multiplexing means, and (B) said amplifier means associated with said own channel.

16. A satellite according to claim 13, wherein each of said distortion linearizers is uniquely associated, in all positions of said switch means, with a corresponding one of said amplifier means.