High power MOSFET with low on-resistance and high breakdown voltage

• US 5,191,396 A
• Filed: 01/30/1989
• Issued: 03/02/1993
• Est. Priority Date: 10/13/1978
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Lidow, Alexander, Herman, Thomas
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/303,818
• Time in Patent Office: 1,492 Days
• Field of Search: 357/23.4, 357/41, 357/43, 357/59
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

Claims

1. A three-terminal power metal oxide silicon field effect transistor device comprising:

a wafer of semiconductor material having first and second opposing semiconductor surfaces;

said wafer of semiconductor material having a relatively lightly doped, one conductivity type major body portion for receiving junctions;

at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first surface to a depth beneath said first surface;

the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first surface location;

first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface locations and extending from said first and second first surface locations to a depth less than said depth of said base regions;

said first and second source regions being laterally spaced along said first surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first surface between each pair of said first and second source regions, respectively, and said common conduction region;

source electrode means located on said first surface, connected to said source regions and comprising a first terminal;

gate insulation layer means on said first surface and disposed at least on said first and second channel regions;

gate electrode means on said gate insulation layer means, overlying said first and second channel regions and comprising a second terminal;

a drain conductive region remote from said common region and extending from said first surface into said major body portion; and

a drain electrode located on said first surface, coupled to said drain conductive region and comprising a third terminal whereby a current path is defined between said source electrode means and said drain electrode which has a first vertical component from said source electrode means through said common conductive region, a lateral component beneath said at least first and second spaced bases and a second vertical component from beneath said at least first and second spaced bases to said drain electrode;

wherein said wafer of semiconductor material further includes a laterally extending relatively thin buried drain region disposed within said drain conductive region and being of said one conductivity type and having a concentration greater than the concentration of said relatively lightly doped major body portion, and extending beneath and spaced from said common conduction region and said at least first and second bases;

said buried drain region portion serving to reduce resistance to lateral current flow between said common conduction region and said drain conductive region.

2. The high power metal oxide silicon field effect transistor device of claim 1, wherein each of said at least first and second spaced base regions of said opposite conductivity type has respective profiles which include relatively shallow depth regions extending from said common region and underlying their said respective first and second source regions, and respective relatively deep, relatively large radius regions extending from said shallow depth regions which are laterally spaced from beneath said respective source regions on the side of said source regions which is away from said common region;

said relatively large radius regions at least partially underlying their said respective source regions.

3. The device of claim 2, wherein said relatively deep regions have a depth of about 4 microns.

4. The device of claim 1, wherein said common region is relatively highly doped, compared to said relatively lightly doped major body portion and extends from said given first surface location to a depth greater than the depth of said source regions, whereby resistance to current flow at the junctures between said first and second channel regions and said common region and between said common region and said relatively lightly doped major body portion is reduced.

5. The high power metal oxide silicon field effect transistor device of claim 1, wherein said wafer of semiconductor material further includes a layer of the opposite conductivity type serving as a substrate layer for the previously mentioned semiconductor regions.

6. The high power metal oxide silicon field effect transistor device of claim 1, wherein said device is formed by D-MOS manufacturing techniques.

7. The device of claim 1, wherein said gate insulation layer means is silicon dioxide.

8. The device of claim 1 wherein said one conductivity type is the n-type and wherein said opposite conductivity type is the p-type.

9. The device of claim 1, wherein said gate electrode means is formed of polysilicon.

10. The device of claim 1, wherein said relatively lightly doped body portion has a resistivity greater than about 2.5 ohm centimeters.