MOS transistor with high breakdown voltage

• US 5,191,401 A
• Filed: 11/07/1991
• Issued: 03/02/1993
• Est. Priority Date: 03/10/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawamura, Ken, Shirai, Koji
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US07/789,444
• Time in Patent Office: 481 Days
• Field of Search: 357/42, 357/41, 357/12, 357/48, 357/23.13, 357/23.8, 357/13, 357/23.3, 357/23.4
• US Class Current: 257/328
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first well of a second conductivity type formed on the semiconductor substrate of the first conductivity type, a first impurity diffusion layer of the first conductivity type formed on the well without contacting the semiconductor substrate, a second impurity diffusion layer of the second conductivity type which surrounds the first impurity diffusion layer and has an impurity concentration which is higher than that of the first impurity diffusion layer, a third impurity diffusion layer of the first conductivity type formed within the second impurity diffusion layer so as to contact neither the semiconductor substrate nor the first impurity diffusion layer, a source electrode connected to both the second impurity diffusion layer and the third impurity diffusion layer, a gate electrode which is formed between the first impurity diffusion layer and the third impurity diffusion layer and formed on the second impurity diffusion layer so as to interpose an insulation film therebetween, a drain electrode connected to the first impurity diffusion layer, and a wiring layer extracted from the drain electrode outside the semiconductor substrate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a plurality of wells of a second conductivity type formed in said semiconductor substrate;

a plurality of FET structure each having a drain electrode, with each of said structures formed in a different one of said wells; and

a wiring layer extracted from said drain electrode outside said semiconductor substrate;

wherein at least one of said FET structure includes;

a first impurity diffusion layer of the first conductivity type formed in said one of said wells without contacting said semiconductor substrate;

a second impurity diffusion layer of the second conductivity type which surrounds said first impurity diffusion layer and has an impurity concentration higher than that of said well;

a third impurity diffusion layer of the first conductivity type formed within said second impurity diffusion layer without contacting said semiconductor substrate and said first impurity diffusion layer, said third impurity diffusion layer being ring-shaped and having a gap therein through which said wiring layer extends;

a source electrode connected to both said second impurity diffusion layer and said third impurity diffusion layer;

a gate electrode formed between said first impurity diffusion layer and said third impurity diffusion layer and formed on said second impurity diffusion layer so as to interpose an insulation film therebetween; and

a drain electrode connected to said first impurity diffusion layer.

2. The semiconductor device according to claim 1, further comprising a fourth impurity diffusion layer connected to said drain electrode, formed in said third impurity diffusion layer and having an impurity concentration which is higher than that of said third impurity diffusion layer.

3. The semiconductor device according to claim 2, further comprising a fifth impurity diffusion layer surrounding said fourth impurity diffusion layer without contacting said second impurity diffusion layer and having an impurity concentration which is higher than that of said third impurity diffusion layer and lower than that of said fourth impurity diffusion layer.

4. The semiconductor device according to claim 3, further comprising a sixth impurity diffusion layer of a second conductivity type surrounding said third impurity diffusion layer and having an impurity concentration which is higher than that of said second impurity diffusion layer, one end of said sixth impurity diffusion layer extending under one end of said gate electrode under said wiring layer.

5. The semiconductor device according to claim 1, wherein said insulation film has a thick portion under said gate electrode and toward a side of said drain electrode.

6. The semiconductor device according to claim 1, further comprising:

a MOS FET of a second conductivity channel type; and

a MOS FET formed next to said MOS FET and on said semiconductor substrate.

7. The semiconductor device according to claim 6, further comprising a fourth impurity diffusion layer connected to said drain electrode, formed in said third impurity diffusion layer and having an impurity concentration which is higher than that of said third impurity diffusion layer.

8. The semiconductor device according to claim 7, further comprising a fifth impurity diffusion layer surrounding said fourth impurity diffusion layer without contacting said second impurity diffusion layer and having an impurity concentration which is higher than that of said third impurity diffusion layer and lower than that of said fourth impurity diffusion layer.

9. The semiconductor device according to claim 8, further comprising a sixth impurity diffusion layer of a second conductivity type surrounding said third impurity diffusion layer and having an impurity concentration which is higher than that of said second impurity diffusion layer, one end of said sixth impurity diffusion layer extending under one end of said gate electrode under said wiring layer.

10. The semiconductor device according to claim 6, wherein said insulation film has a thick portion under said gate electrode and toward a side of said drain electrode.

11. The semiconductor device according to claim 6, further comprising a MOSFET of a second conductivity channel type and of a low breakdown voltage formed on said semiconductor substrate.

12. The semiconductor device according to claim 6, further comprising a MOSFET of a first conductivity channel type and of a low breakdown voltage formed on said semiconductor substrate.

13. The semiconductor device according to claim 1, wherein said first conductivity type is a P-type.

14. The semiconductor device according to claim 1, wherein said first conductivity type is an N-type.