Video noise reducer with detection of both total and temporal picture changes

• US 5,191,419 A
• Filed: 04/24/1991
• Issued: 03/02/1993
• Est. Priority Date: 04/27/1990
• Status: Expired due to Fees

• Current Assignee: BTS Broadcast Television Systems GmbH
• Original Assignee: BTS Broadcast Television Systems GmbH
• Inventors: Wischermann, Gerhard
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Murrell, Jeffrey S.
• Application Number:
  US07/690,620
• Time in Patent Office: 678 Days
• Field of Search: 358/167, 358/36, 358/105, 358/166
• US Class Current: 348/701
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Abstract

A video noise reducer comprises a full picture memory and provides comparison of corresponding pixels of undelayed and delayed video signals, in which the delayed signal is fed back and mixed which is the undelayed signal at a controllable fader fading factor controlled by the absolute value difference between compared pixels subjected to filtering and other processing. In this noise reducer pixel comparison is elaborated to provide a signal designating the sign of the difference and a temporal (non-spatial) motion detector checks for the predominance of designations of one sign (and the rarity of designations of the other sign) in order to establish the presence of a fading procedure which must not be mistakenly interpreted as a detection of motion in the picture content. The temporal motion detector can be constituted so that isolated designations of a sign opposite to the preponderant sign of a succession of designations of the same sign cannot prevent the recognition of the presence of a fading procedure.

Claims

1. Apparatus including a fader circuit (C) for reducing noise in a first video signal (A) provided to a first input of said fader circuit (C), said fader circuit having an output, said apparatus having a write-read memory (ST) connected in circuit for delaying a second video signal for essentially a full picture period to produce in a read-out of said write-read memory a delayed second video signal (B) said output of said fader circuit (C) providing said second video signal and being connected to an input of said write-read memory and having said first input and a second input connected for fading together said first video signal (A) and said delayed second video signal (B) at a controllable fading factor (k), a total motion detector (E'"'"', P) including a comparator (E'"'"') connected for comparing corresponding pixels of said delayed second video signal (B) and said first video signal (A) and a control circuit (P), having a preliminary filter (F) for eliminating high frequency noise components, of which an input is connected to an output of said comparator (E'"'"'), wherein said filter output produces a signal (M) representative of the absolute value difference between said corresponding pixels, said control circuit also including a read-only memory (T'"'"') for modifying said fading factor in response to said filter output signal (M) so that, with increasing total motion in a scene defined by said first video signal, the contribution of said delayed second video signal to the output of said fader circuit is reduced, characterized in that

said comparator (E'"'"') has a second output (±

) for a signal designating the sign of every said difference between corresponding pixels found in comparison of said first video signal and said delayed second video signal by said comparator, in addition to said output of said comparator connected to said control circuit (P);

said read-only memory (T'"'"') of said total motion detector is connected for being addressed jointly by output (M) from said preliminary filter (F) and by at least first and second address signal values, said first address signal value (S1) being a motion-signal-effectiveness threshold value, and

a temporal motion detecting logic circuit (TD, TD'"'"' TD") having an input connected to said output (±

) for said sign designating signal of said comparator and an output connected to supply said second address signal value (S3) to an address input of said read-only memory, for at least partially preventing the reduction of the fading factor applied in said fader circuit (C) when designations of the same sign are predominant among sequential sign designations provided by said sign designating signal.

2. The apparatus of claim 1, wherein said temporal motion detecting logic circuit (TD) includes a numerical storage register, connected in circuit for having its numerical content altered in a first direction by a first determined amount when one of said sign designations provided by said sign designating signal follows another of said sign designations which is of the same sign and for having its numerical content altered in a second direction opposite to said first direction by a second predetermined amount when one of said sign designations provided by said sign designating signal follows another of said sign designations which is of the opposite sign, said storage register having an output (S3), connected to said address input of said read-only memory (T'"'"') for said second address signal value, for modifying the degree of dependence of said fading factor on detected total motion in accordance with the current numerical content of said register.

3. The apparatus of claim 1, wherein said temporal motion detecting logic circuit has an initial state (0) and is capable of taking on other states (91-100;

101-200) in response to said sequential sign designations provided by said sign designating signal for producing a state of said logic circuit more remote from said initial state when said sign designations an indication are all of the same sign and for producing a state of said logic circuit closer to said initial state when one of said sign designations follows another of said sign designations which is of an opposite sign, said temporal motion detecting logical circuit output being dependent on how far from said initial state is the current state of said temporal motion detecting logic circuit.

4. The apparatus of claim 3, wherein said temporal motion detecting logic circuit is connected for producing a one-step change of state of the logic circuit away from said initial state in response to one of said sign designations that follows another of said sign designations which is of the same sign and for producing a multiple step change of state towards said initial state in response to one of said sign designations which follows another of said sign designations which is of the opposite sign.

5. The apparatus of claim 4, wherein said multiple step change is a four-step change.

6. The apparatus of claim 3, wherein said temporal motion detecting logic circuit is connected for producing a one-step change of state away from said initial state in response to one of said sign designations that follows another of said sign designations which is of the same sign and for producing a transfer to the initial state (0) in response to one of said sign designations which follows another of said sign designation which is of the opposite sign.

7. The apparatus of claim 3, wherein said read-only memory (T'"'"') is connected for being addressed as aforesaid, jointly with a contribution of a third signal value (S2), supplied at a third additional input of said read-only memory for representation of the degree of noise reduction for still picture content and wherein said read-only memory (T'"'"') contains a stored table and also has at least one fading factor data output for data from said table which are a function of an output of the total motion detector (P) for different values of the output of said temporal motion detecting logic circuit (TD, TD'"'"', TD") and also a function of different values of said first (S1) and third (S2) signal values, which are predetermined setting values, supplied respectively to said first and third additional inputs of said read-only memory (T'"'"').

8. The apparatus of claim 1, wherein said control circuit (P) for modifying said fading factor in response to said total motion detector is deigned to produce a fading factor which is substantially independent of said total motion detector up to a threshold value of detected total motion set by said first signal value (S1) and, beyond said threshold value, is reduced with increasing detection of total motion, and wherein said temporal motion detecting logic circuit (TD, TD'"'"', TD") produces an output (S3) supplied to said read-only memory (T'"'"') at said second additional input thereof which has the effect, by virtue of contents of said read-only memory, of raising said threshold value when sign designations of one sign are predominant among said sign designations of said sign designating signal (S±

).

9. The apparatus of claim 1, wherein said read-only memory (T'"'"') is connected for being addressed as aforesaid, jointly with a contribution of a third signal value (S2), supplied at a third additional input of said read-only memory for representation of the degree of noise reduction for still picture content and wherein said read-only (T'"'"') contains a stored table and also has at least one fading factor data output for data from said table which are a function of an output of the total motion detector (P) for different values of the output of said temporal motion detection logic circuit (TD, TD'"'"', TD") and further for different values of said first (S1) and third (S2) signal values, which are predetermined setting values, supplied respectively to said first and third additional inputs of said read-only memory (T'"'"').

10. The apparatus of claim 9, wherein said temporal motion detecting logic circuit (TD) includes a numerical storage register, connected in circuit for having its numerical content altered in a first direction by a first determined amount when one of said sign designations provided by said sign designating signal follows another of said sign designations which is of the same sign and for having its numerical content altered in a second direction opposite to said first direction by a second predetermined amount when one of said sign designations provided by said sign designating signal follows another of said sign designations which is of the opposite sign, said storage register having an output (S3), connected to said input of said control circuit for said second additional signal value, for modifying the degree of dependence of said fading factor on detected total motion in accordance with the current numerical content of said register.

11. The apparatus of claim 9, wherein said temporal motion detecting logic circuit (TD'"'"') is connected for producing a one-step change of logic circuit state away from said initial state in response to one of said sign designations that follows another of said sign designations which is of the same sign and for producing a multiple step change of state towards said initial state in response to one of said sign designations which follows another of said sign designation which is of the opposite sign.

12. The apparatus of claim 11, wherein said multiple step change is a four-step change.

13. The apparatus of claim 9, wherein said temporal motion detecting logic circuit is connected for producing a one-step change of state away from said initial state in response to one of said sign designations that follows another of said sign designation which is of the same sign and for producing a transfer to the initial state (0) in response to one of said sign designations which follows another of said sign designation which is of the opposite sign.

14. The apparatus of claim 9, wherein said control circuit (P) for modifying said fading factor in response to said total motion detector is designed to produce a fading factor which is substantially independent of said total motion detector up to a threshold value of detected total motion set by said first signal value (S1) and, beyond said threshold value, is reduced with increasing detection of total motion, and wherein said temporal motion detecting logic circuit (TD, TD'"'"', TD") produces an output (S3) supplied to said read-only memory (T'"'"') at said second additional input thereof which has the effect, by virtue of contents of said read-only memory, of raising said threshold value when sign designations of one sign are predominant among said sign designations of said sign designating signal (S±

).