Current sharing control in a parallel inverter system

• US 5,191,519 A
• Filed: 03/26/1992
• Issued: 03/02/1993
• Est. Priority Date: 03/27/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawakami, Kazuto
• Primary Examiner(s): Stephan, Steven L.
• Assistant Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US07/858,064
• Time in Patent Office: 341 Days
• Field of Search: 363/71, 363/95 X, 363/96, 363/97, 363/98
• US Class Current: 363/71
• CPC Class Codes: H02J 3/46 Controlling of the sharing of output between the generators, converters, or transformers
• CPC Class Codes: H02M 7/493 the static converters being arranged for operation in parallel

Abstract

This inverter system is directed to an inverter system in which a plurality of inverters adapted for generating output voltages corresponding to a voltage reference and a frequency reference respectively given through voltage controllers and frequency controllers are operated in parallel. In this inverter system, a difference between an output current of a corresponding inverter and output currents of other inverters is detected. By implementing the d-q axis orthogonal coordinate transform processing to that current difference, a first correction signal relating to the frequency of an output voltage of that inverter and a second correction signal relating to the amplitude of the output voltage thereof are provided.

Claims

1. An inverter system including a plurality of inverters connected in parallel,

each of said plurality of inverters comprising:

current detection means for detecting an output current of a corresponding inverter;

voltage control means for generating a voltage control signal corresponding to a difference between a voltage reference and an actual voltage of said corresponding inverter;

frequency control means adapted for generating a frequency control signal corresponding to a difference between a frequency reference and an actual frequency of said corresponding inverter;

current difference formation means for forming a current difference signal relating to said corresponding inverter on the basis of a detected result of said current detection means;

d-q axis orthogonal coordinate transform means for transforming a current difference signal formed by said current difference detection means to a signal on the d-q axis orthogonal coordinate system, thus to form a first correction signal relating to the frequency of an output voltage of said corresponding inverter and a second correction signal relating to the amplitude of said output voltage thereof;

first correction means for correcting said frequency control signal by said first correction signal;

second correction means for correcting said voltage control signal by said second correction signal; and

means for controlling said corresponding inverter in accordance with outputs from said first correction means and said second correction means.

2. An inverter system as set forth in claim 1, wherein said frequency control means is comprised of a Phase Locked Loop.

3. An inverter system as set forth in claim 2, wherein said Phase Locked Loop is comprised of a phase error detector, a low-pass filter, and a voltage controlled oscillator.

4. An inverter system as set forth in claim 3, wherein said first correction signal is applied to the input terminal of said low-pass filter.

5. An inverter system as set forth in claim 3, wherein said first correction signal is applied to the input terminal of said voltage controlled oscillator.

6. An inverter system as set forth in claim 3, wherein said first correction signal is applied to both the input terminal of said low-pass filter and the input terminal of said voltage controlled oscillator.

7. An inverter system as set forth in claim 1, wherein said voltage control means is comprised of a PI action controller.

8. An inverter system as set forth in claim 7, wherein said second correction signal is applied to the input terminal of said PI action controller.

9. An inverter system as set forth in claim 7, wherein said second correction signal is applied to the output terminal of said PI action controller.

10. An inverter system as set forth in claim 7, wherein said second correction signal is applied to both the input terminal and the output terminal of said PI action controller.

11. An inverter system as set forth in claim 1, wherein said d-q axis orthogonal coordinate transform means is comprised of d-axis coordinate transform means and q-axis coordinate transform means, said d-axis coordinate transform means being operative to form, as its d-axis component, a first correction signal relating to the frequency of an output voltage of said inverter on the basis of said current difference signal, said q-axis coordinate transform means being operative to form, as its q-axis component, a second correction signal relating to the amplitude of an output voltage of said inverter on the basis of said current difference signal.

12. An inverter system as set forth in claim 1, wherein an a.c. filter is provided on the output side of each inverter, said current detection means being provided on the output side of said a.c. filter.

13. An inverter system as set forth in claim 1, wherein an a.c. filter is provided on the output side of each inverter, said current detection means being provided on the input side of said a.c. filter.