Method and apparatus for providing high performance interconnection between interface circuits coupled to information buses

• US 5,191,581 A
• Filed: 12/07/1990
• Issued: 03/02/1993
• Est. Priority Date: 12/07/1990
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Hudnall, Richard E., Hunt, Philip G., Woodbury, Mark P.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): KIZOU, HASSAN
• Application Number:
  US07/623,504
• Time in Patent Office: 816 Days
• Field of Search: 370/85.1, 370/85.11, 370/85.13, 370/85.14, 370/85.9, 370/67, 307/455, 307/456, 395/275
• US Class Current: 370/364
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

Methods and apparatus are provided for interconnecting first and second information buses each having a plurality of data lines. A pair of unidirectional information paths each consisting of twisted-pair cables are provided, along with a 25 MHz strobe. Information is transmitted using pseudo-ECL signal levels. A pair of clock differential receiver circuits is provided such that data is transferred over the interconnect bus using both the rising and falling edges of the transmitted clock signal and transferred from one bus to another at a rate of 50 MHz.

Claims

1. Apparatus for interconnecting first and second interface circuits respectively coupled to first and second information buses each having a plurality of data lines, the apparatus comprising:

first and second unidirectional information paths each having conductors for conducting a plurality of data signals, each of the first and second information paths conducting a number of data signals less than the number of data lines in at least one of the information buses;

a first interconnect module for coupling to the first interface circuit, the first interconnect module comprising a first pair of registers each for respectively and simultaneously receiving a set of a first pair of sets of information from the first interface circuit, a first multiplexer for sequentially transferring each set of the first pair of sets of information bits from the first pair of registers over the data lines of the first information path, and a first connector coupled to the first multiplexer;

a second interconnect module for coupling to the second interface circuit, the second interconnect module comprising a second pair of registers each for respectively supplying a set of the first pair of sets of information bits to the second interface circuit, a second connector removably connected to the first connector, and first demultiplexer means coupled to the second connector for receiving the first pair of sets of information bits sequentially transferred by the first multiplexer and for respectively supplying the first pair of sets of information bits to the second pair of registers;

a third interconnect module for coupling to the second interface circuit and comprising a third pair of registers each for respectively and simultaneously receiving a set of a second pair of sets of information bits from the second interface circuit, a second multiplexer coupled to the second connector for sequentially transferring each set of the second pair of sets of information bits from the third pair of registers over the data lines of the second information path; and

a fourth interconnect module for coupling to the first interface circuit and comprising a fourth pair of registers each for respectively and simultaneously supplying a set of the second pair of sets of information bits to the first interface circuit, and second demultiplexer means coupled to the first connector for receiving the second pair of sets of information bits sequentially transferred by the second multiplexer and for respectively supplying the second pair of sets of information bits to the fourth pair of registers.

2. Apparatus as recited in claim 1, comprising control means, operatively coupled to the first, second, third, and fourth interconnect modules, for initiating transfer of information from the first interface circuit to the second interface circuit in response to commands received from the first and second interface circuits.

3. Apparatus as recited in claim 1, comprising:

a first twisted-pair cable included in the first information path and connected to the first connector;

first ECL differential converter means coupled between the first multiplexer and the first twisted-pair cable for converting TTL-compatible signals into ECL-compatible differential signals for transmission over the twisted-pair first cable;

a second twisted-pair cable included in the first information path and connected to the second connector;

a third twisted-pair cable included in the second information path and connected to the second connector;

a first ECL differential receiver, included in the first demultiplexer means and coupled between the second twisted pair cable and the second pair of registers, for converting ECL-compatible differential signals received over the second twisted-pair cable to TTL-compatible signals;

second ECL differential converter means coupled between the second multiplexer and the third twisted-pair cable for converting TTL-compatible signals into ECL-compatible differential signals for transmission over the third cable;

a fourth twisted-pair cable included in the second information path and connected to the first connector; and

a second ECL differential receiver, included in the second demultiplexer means and coupled between the fourth twisted pair cable and the fourth pair of registers, for converting ECL-compatible differential signals received over the fourth cable to TTL-compatible signals.

4. Apparatus as recited in claim 1, comprising:

means for respectively supplying first and second clock signals respectively having first and second clock rates to the first and third pairs of registers to store information in the first and third pairs of registers; and

means for respectively supplying third and fourth clock signals, respectively having third and fourth clock rates respectively twice the first and second clock rates, to the first and second multiplexers so as to respectively transfer information over the first and second information paths at the third and fourth clock rates.

5. Apparatus as recited in claim 4, comprising means for respectively transmitting the first and second clock signals over the first and second information paths, means for receiving the transmitted clock signals, and means respectively coupled to the second and fourth pairs of registers for latching the transferred information into the second and fourth pairs of registers on both the rising and falling edges of the transmitted clock signals.

6. Apparatus as recited in claim 5, wherein the means for supplying first and second clock signals comprises divider means for respectively dividing the third and fourth clock signals down to the first and second clock rates to produce the first and second clock signals and for respectively supplying the first and second clock signals over the first and second information paths;

and

first and second clock multiplexer means for respectively converting the transmitted first and second clock signals to transfer clock signals supplied to the second and fourth pairs of registers to respectively transfer information from the second and fourth pairs of registers to the second and first interface circuits at the third and fourth clock rates.

7. Apparatus as recited in claim 6, wherein:

the divider means comprises a first 2;

1 divider circuit for dividing the third clock signal;

the means for supplying first and second clock signals comprises a first delay circuit coupled to the first divider circuit to receive the divided third clock signal, and a first clock signal ECL differential driver circuit coupled between the first delay circuit and the first connector to supply the divided third clock signal to the first information path as an ECL-compatible differential signal;

the first clock multiplexer means comprises first and second clock signal ECL differential receiver circuits coupled to the second connector and respectively coupled to first and second registers of the second register pair to supply the transmitted first clock signal respectively to the first and second registers of the second register pair as non-inverted and inverted transfer clock signals each constituting a single-ended TTL-compatible signal;

the divider means further comprises a second 2;

1 divider circuit for dividing the fourth clock signal;

the means for supplying first and second clock signals further comprises a second delay circuit coupled to the second divider circuit to receive the divided fourth clock signal, and a second clock signal ECL differential driver coupled between the second delay circuit and the second connector to supply the divided fourth clock signal to the second information path as an ECL-compatible differential signal; and

the second clock multiplexer means comprises third and fourth clock signal ECL differential receiver circuits coupled to the first connector and respectively coupled to first and second registers of the fourth register pair to supply the transmitted second clock signal respectively to the first and second registers of the fourth register pair as non-inverted and inverted transfer clock signals each constituting a single-ended TTL-compatible signal.

8. Apparatus as recited in claim 7, wherein the first and second delay circuits each have a delay period equal to one-half the period of the third and fourth clock signals.

9. Apparatus as recited in claim 7, wherein:

the first clock signal ECL differential driver comprises a non-inverted output and an inverted output;

the first clock signal ECL differential receiver circuit comprises a non-inverted input coupled, via the first information path, to the non-inverted output of the first clock signal ECL differential driver circuit;

an inverted input coupled, via the first information path, to the inverted output of the first clock signal ECL differential driver circuit; and

an output coupled to the first register of the second pair of registers;

the second clock signal ECL differential receiver circuit comprises an inverted input coupled, via the first information path, to the non-inverted output of the first clock signal ECL differential driver circuit;

a non-inverted input coupled, via the first information path, to the inverted output of the first clock signal ECL differential driver circuit; and

an output coupled to the second register of the second pair of registers;

the second clock signal ECL differential driver comprises a non-inverted output and an inverted output;

the third clock signal ECL differential receiver circuit comprises a non-inverted input coupled, via the second information path, to the non-inverted output of the first clock signal ECL differential driver circuit;

an inverted input coupled, via the second information path, to the inverted output of the second clock signal ECL differential driver circuit; and

an output coupled to the first register of the fourth pair of registers; and

the fourth clock signal ECL differential receiver circuit comprises an inverted input coupled, via the second information path, to the non-inverted output of the second clock signal ECL differential driver circuit;

a non-inverted input coupled, via the second information path, to the inverted output of the second clock signal ECL differential driver circuit; and

an output coupled to the second register of the fourth pair of registers.

10. Apparatus as recited in claim 1, comprising:

means for receiving a BLOCK DATA READ command from the second interface circuit to request data from the first interface circuit, and for transferring the BLOCK DATA READ command to the first interface circuit;

means in the first interconnect module for sending a BLOCK DATA READ ACKNOWLEDGE signal and the requested data to the second interconnect module in response to a BLOCK DATA READ command from the second interface circuit and for setting a BLOCK DATA READ flag upon sending of the BLOCK DATA READ ACKNOWLEDGE signal;

means in the first interconnect module for preventing receipt of commands from the first interface circuit when the BLOCK DATA READ flag is set;

means in the second interconnect module for temporarily storing data received in response to the BLOCK DATA READ command, for purging the storage means, and for transmitting a PURGE COMPLETE command to the fourth interconnect module when purging of the storage means is complete; and

means for resetting the BLOCK DATA READ flag when a PURGE COMPLETE command is received by the fourth interconnect module.

11. Apparatus as recited in claim 1, comprising:

means for receiving a DATA TRANSFER command from the second interface circuit, for transmitting the DATA TRANSFER command to the first interface circuit over the second information path, for setting a DATA TRANSFER flag upon transfer of the DATA TRANSFER command, and for preventing transmission over the second information path of commands received by the third interconnect module from the second interface circuit when the DATA TRANSFER flag is set;

means for generating a DATA TRANSFER ACKNOWLEDGE signal in response to receipt of a DATA TRANSFER command by the fourth interconnect module and for sending the DATA TRANSFER ACKNOWLEDGE signal to the second interconnect module; and

means for resetting the DATA TRANSFER flag upon receipt of the DATA TRANSFER ACKNOWLEDGE signal by the second interconnect module.

12. Apparatus for interconnecting an interface circuit, coupled to a first information bus, to an adapter module coupled to a second information bus, each of the information buses having a plurality of data lines, the apparatus comprising:

first and second unidirectional information paths each having conductors for conducting a plurality of data signals, each of said first and second information paths conducting a number of data signals less than the number of data lines in at least one of the information buses;

a transmitter interconnect module for coupling to the interface circuit, the transmitter interconnect module comprising a first pair of registers each for respectively and simultaneously receiving a set of a first pair of sets of information bits from the interface circuit, and a multiplexer for sequentially transferring each set of the first pair of sets of information bits from the first pair of registers over the data lines of the first information path, and a connector coupled to the multiplexer; and

a receiver interconnect module for coupling to the interface circuit, the receiver interconnect module comprising a second pair of registers each for respectively and simultaneously supplying a set of a second pair of sets of information bits to the interface circuit, and demultiplexer means coupled to the connector for sequentially receiving the second pair of sets of information bits over the second information path and for respectively supplying the second pair of sets of information bits to the second pair of registers; and

control means for initiating transfer of information bits from the interface circuit to the adapter module in response to commands received from the interface circuit, and for responding to requests from the adapter module to the interface circuit.

13. Apparatus as recited in claim 12, comprising:

a first twisted-pair cable included in the first information path and connected to the connector;

ECL differential converter means coupled between the multiplexer and the first twisted-pair cable for converting TTL-compatible signals into ECL-compatible differential signals for transmission over the first cable;

a second twisted pair cable included in the second information path and connected to the connector; and

an ECL differential receiver, included in the demultiplexer and coupled between the second twisted pair cable and the second pair of registers, for converting ECL-compatible differential signals received over the second cable to TTL-compatible signals.

14. Apparatus as recited in claim 12, comprising:

means for supplying a first clock signal having a first clock rate to the first pair of registers to store information in the first pair of registers;

means for supplying a second clock signal, having a second clock rate twice the first clock rate, to the multiplexer; and

means responsive to the second clock signal for transferring information over the first information path at the second clock rate.

15. Apparatus as recited in claim 14, comprising means for transmitting the first clock signal over the first information path, means for receiving from the adapter module a transmitted third clock signal having a rate equal to the first clock signal, and means coupled to the second pair of registers for latching the received information into the second pair of registers on both the rising and falling edge of the third clock signal.

16. Apparatus as recited in claim 15, wherein the means for supplying the first clock signal comprises divider means for respectively dividing the second clock signal down to the first clock rate to produce the first clock signal and for respectively supplying the first clock signal over the first information path;

and

clock multiplexer means for converting the received third clock signal to transfer clock signals supplied to the second pair of registers to transfer information from the second pair of registers to the interface circuit at the first clock rate.

17. Apparatus as recited in claim 16, wherein:

the divider means comprises a 2;

1 divider circuit for dividing the second clock signal;

the means for supplying the first clock signal comprises a delay circuit coupled to the divider circuits to receive the divided second clock signal, and a clock signal ECL differential driver circuit coupled between the delay circuit and the connector to supply the divided second clock signal to the first information path as an ECL-compatible differential signal; and

the clock multiplexer means comprises first and second clock signal ECL differential receiver circuits coupled to the connector and respectively coupled to first and second registers of the second register pair to supply the received third clock signal respectively to the first and second registers of the second register pair as non-inverted and inverted transfer clock signals each constituting a single-ended TTL-compatible signal.

18. Apparatus as recited in claim 17, wherein the delay circuit has a delay period equal to one-half the period of the second clock signal.

19. Apparatus as recited in claim 17, wherein:

the clock signal ECL differential driver comprises a non-inverted output and an inverted output;

the first clock signal ECL differential receiver circuit comprises a non-inverted input for coupling, via the second information path, to a non-inverted output of an associated clock signal ECL differential driver circuit of the interconnect adapter module;

an inverted input for coupling, via the second information path, to an inverted output of the associated clock signal ECL differential driver circuit; and

an output coupled to the first register of the second pair of registers; and

the second clock signal ECL differential receiver circuit comprises an inverted input for coupling, via the second information path, to the non-inverted output of the associated clock signal ECL differential driver circuit;

a non-inverted input for coupling, via the second information path, to the inverted output of the associated clock signal ECL differential driver circuit; and

an output coupled to the second register of the second pair of registers.

20. Apparatus as recited in claim 12, comprising:

means for receiving a BLOCK DATA READ command from the adapter module to request data from the interface circuit, and for transferring the BLOCK DATA READ command to the interface circuit;

means in the transmitter interconnect module for sending a BLOCK DATA READ ACKNOWLEDGE signal and the requested data to the adapter module in response to a BLOCK DATA READ command from the interface circuit and for setting a BLOCK DATA READ flag upon sending of the BLOCK DATA READ ACKNOWLEDGE signal;

means in the transmitter interconnect module for preventing receipt of commands from the interface circuit when the BLOCK DATA READ flag is set; and

means for resetting the BLOCK DATA READ flag when a PURGE COMPLETE command is received from the adapter module by the receiver interconnect module.

21. A method for interconnecting first and second interface circuits respectively coupled to first and second information buses each having a plurality of data lines, the method comprising the steps of:

respectively and simultaneously receiving a first pair of sets of information bits from the first interface circuit into a first pair of registers;

operating a first multiplexer to sequentially transfer each set of the first pair of sets of information bits from the first pair of registers over conductors of a first information path;

respectively receiving, in a second pair of registers, the first pair of sets of information bits sequentially transferred by the first multiplexer;

respectively and simultaneously supplying the first pair of sets of information bits from the second pair of registers to the second interface circuit;

respectively and simultaneously receiving a second pair of sets of information bits from the second interface circuit into a third pair of registers;

operating a second multiplexer to sequentially transfer each set of the second pair of sets of information bits from the third pair of registers over conductors of a second information path;

respectively receiving, in a fourth pair of registers, the second pair of sets of information bits sequentially transferred by the second multiplexer; and

respectively and simultaneously supplying the second pair of sets of information bits from the fourth pair of registers to the first interface circuit.

22. A method for interconnecting an interface circuit, coupled to a first information bus, to an adapter module coupled to a second information bus, each of the information buses having a plurality of data lines, the method comprising the steps of:

respectively and simultaneously receiving a first pair of sets of information bits from the interface circuit into a first pair of registers;

operating a multiplexer to sequentially transfer each set of the first pair of sets of information bits from the first pair of registers over data lines of a first information path;

respectively receiving in sequence, in a second pair of registers from a second information path, a second pair of sets of information bits from the adapter module; and

respectively and simultaneously supplying the second pair of sets of information bits from the second pair of registers to the interface circuit.

23. A method as recited in claim 22 wherein the step of respectively receiving in sequence, in a second pair of registers from a second information path, a second pair of sets of information bits from the adapter module comprises the substep of latching the received information into the second pair of registers on both the rising and falling edges of a clock signal.

24. A method for interconnecting an interface circuit, coupled to a first information bus, to an adapter module coupled to a second information bus, each of the information buses having a plurality of data lines, the method comprising the steps of:

respectively and simultaneously receiving a first pair of sets of information bits from the interface circuit into a first pair of registers;

operating a multiplexer to sequentially transfer each set of the first pair of sets of information bits from the first pair of registers over data lines of a first unidirectional information path;

respectively receiving in sequence, in a second path of registers from a second unidirectional information path, a second pair of sets of information bits from the adapter module; and

respectively and simultaneously supplying the second pair of sets of information bits from the second pair of registers to the interface circuit.