Neuron unit and neuron unit network
First Claim
1. A neuron unit for simultaneously processing a plurality of binary input signals and for outputting an output signal which is indicative of a result of the processing, said neuron unit comprising:
- a plurality of input lines for receiving binary input signals which undergo transitions with time;
first and second memory means for storing weighting coefficients;
first gate means for successively obtaining a logical product of one of said binary input signals received from said input lines and a corresponding one of the weighting coefficients read out from said first memory means for each of said binary input signals;
second gate means for successively obtaining a logical product of one of said binary input signals received from s id input lines and a corresponding one of the weighting coefficients read out from said second memory means for each of said binary input signals;
third gate means for obtaining a logical sum of logical products output from said first gate means;
fourth gate means for obtaining a logical sum of logical products output from said second gate means; and
output means including an inverter for inverting the logical sum output from said fourth gate means and a gate for obtaining one of a logical product and a logical sum of the logical sum output from said third gate means and an inverted logical sum output from said inverter, said gate outputting an output signal of said neuron unit.
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Abstract
A neuron unit simultaneously processes a plurality of binary input signals. The neuron unit includes input lines for receiving input signals which undergo transitions with time, first and second memories for storing weighting coefficients, a first gate for successively obtaining a logical product of one of the input signals and a corresponding one of the weighting coefficients read out from the first memory for each of the first input signals, a second gate for successively obtaining a logical product of one of the input signals and a corresponding one of the weighting coefficients read out from the second memory for each of the second input signals, a third gate for obtaining a logical sum of logical products output from the first gate, a fourth gate for obtaining a logical sum of logical products output from the second gate, and an output part including an inverter for inverting the logical sum output from the fourth gate and a gate for obtaining one of a logical product and a logical sum of the logical sum output from the third gate and an inverted logical sum output from the inverter. This gate outputs an output signal of the neuron unit.
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Citations
9 Claims
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1. A neuron unit for simultaneously processing a plurality of binary input signals and for outputting an output signal which is indicative of a result of the processing, said neuron unit comprising:
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a plurality of input lines for receiving binary input signals which undergo transitions with time; first and second memory means for storing weighting coefficients; first gate means for successively obtaining a logical product of one of said binary input signals received from said input lines and a corresponding one of the weighting coefficients read out from said first memory means for each of said binary input signals; second gate means for successively obtaining a logical product of one of said binary input signals received from s id input lines and a corresponding one of the weighting coefficients read out from said second memory means for each of said binary input signals; third gate means for obtaining a logical sum of logical products output from said first gate means; fourth gate means for obtaining a logical sum of logical products output from said second gate means; and output means including an inverter for inverting the logical sum output from said fourth gate means and a gate for obtaining one of a logical product and a logical sum of the logical sum output from said third gate means and an inverted logical sum output from said inverter, said gate outputting an output signal of said neuron unit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A neuron unit network comprising:
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a plurality of neuron units which are coupled to form a hierarchical structure which has a plurality of layers; and a plurality of signal lines coupling outputs of arbitrary neuron units in one layer of the hierarchical structure to inputs of arbitrary neuron units in another layer of the hierarchical structure, each of said neuron units simultaneously processing a plurality of binary input signals and outputting an output signal which is indicative of a result of the processing, said neuron unit comprising a plurality of input lines for receiving binary input signals which undergo transitions with time, first and second memory means for storing weighting coefficients, first gate means for successively obtaining a logical product of one of said binary input signals received from said input lines and a corresponding one of the weighting coefficients read out from said first memory means for each of said binary input signals, second gate means for successively obtaining a logical product of one of said binary input signals received from said input lines and a corresponding one of the weighting coefficients read out from said second memory means for each of said binary input signals, third gate means for obtaining a logical sum of logical products output from said first gate means, fourth gate means for obtaining a logical sum of logical products output from said second gate means, and output means including an inverter for inverting the logical sum output from said fourth gate means and a gate for obtaining one of a logical product and a logical sum of the logical sum output from said third gate means and an inverted logical sum output from said inverter, said gate outputting an output signal of said neuron unit. - View Dependent Claims (8, 9)
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Specification