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Neuron unit and neuron unit network

  • US 5,191,637 A
  • Filed: 03/24/1992
  • Issued: 03/02/1993
  • Est. Priority Date: 07/12/1989
  • Status: Expired due to Term
First Claim
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1. A neuron unit for simultaneously processing a plurality of binary input signals and for outputting an output signal which is indicative of a result of the processing, said neuron unit comprising:

  • a plurality of input lines for receiving binary input signals which undergo transitions with time;

    first and second memory means for storing weighting coefficients;

    first gate means for successively obtaining a logical product of one of said binary input signals received from said input lines and a corresponding one of the weighting coefficients read out from said first memory means for each of said binary input signals;

    second gate means for successively obtaining a logical product of one of said binary input signals received from s id input lines and a corresponding one of the weighting coefficients read out from said second memory means for each of said binary input signals;

    third gate means for obtaining a logical sum of logical products output from said first gate means;

    fourth gate means for obtaining a logical sum of logical products output from said second gate means; and

    output means including an inverter for inverting the logical sum output from said fourth gate means and a gate for obtaining one of a logical product and a logical sum of the logical sum output from said third gate means and an inverted logical sum output from said inverter, said gate outputting an output signal of said neuron unit.

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