Method of making a digital flexure beam accelerometer

• US 5,192,395 A
• Filed: 10/12/1990
• Issued: 03/09/1993
• Est. Priority Date: 10/12/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sampsell, Jeffrey B., Boysel, Robert M.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US07/596,841
• Time in Patent Office: 879 Days
• Field of Search: 156/643, 156/644, 156/645, 156/652, 156/653, 156/655, 156/656, 156/657, 156/659.1, 156/662, 156/668, 73/517 R, 73/517 AV
• US Class Current: 216/13
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 3/0002 Arrangements for avoiding sticking of the flexible or moving parts
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/135 by making use of contacts which are actuated by a movable inertial mass

Abstract

It is possible to determine acceleration using an array of micro-machined elements. The invention described herein details how to do so by fabricating an array of structures with a substrate, addressing circuitry, a spacer layer forming a well over the addressing circuitry, and a deflection element over the well. The deflection elements are configured so each element is deflected by a higher acceleration. The invention also shows one embodiment of the invention.

Claims

1. A process for fabrication of sensor elements comprising the following:

a) forming a ground plane layer upon a substrate;

b) fabricating addressing circuitry and electrical contacts upon said ground plane;

c) spinning a spacer layer upon the entire substrate;

d) depositing a layer of thin metal upon said spacer layer;

e) patterning said thin metal layer;

g) depositing a layer of heavy metal upon said thin metal layer;

h) patterning and forming said heavy metal layer so each sensor element has a different mass;

i) dividing said substrate into individual chips; and

j) undercutting said spacer layer.

2. The process of claim 1 wherein said substrate is silicon.

3. The process of claim 1 wherein said addressing circuitry is CMOS and said electrical contacts are oxide.

4. The process of claim 1 wherein said spacer is a polymer.

5. The process of claim 1 wherein said thin metal is aluminum.

6. The process of claim 1 wherein said undercutting is a plasma etch.

7. The process of claim 1 wherein said heavy metal is tungsten.

8. The process of claim 1 wherein said patterning of the thin metal layer is done photolithographically.