Method of making field effect transistor
First Claim
1. A method of making a field effect transistor including:
- depositing on a semi-insulating substrate a semiconductor layer of a first conductivity type;
forming a channel of a second conductivity type opposite from said first conductivity type in said substrate, thereby forming a pn junction with said layer;
disposing a metallic gate electrode on said layer opposite said channel; and
forming spaced apart source and drain regions of said second conductivity type in said layer, extending into said substrate, and contacting said channel, said source and drain regions lying on opposite sides of said gate electrode.
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Abstract
A field effect transistor including a semi-insulating semiconductor substrate, a first conductivity type semiconductor layer disposed on the substrate and forming a heterojunction with the substrate, second conductivity type spaced apart source and drain regions extending through the layer into the substrate, a metallic gate disposed on the layer between the source and drain regions, and a second conductivity type channel disposed in the substrate extending between the source and drain regions and forming a pn heterojunction with the layer for reducing leakage current from the channel to the gate. The second conductivity type channel is produced by ion implantation, and the implantation conditions are controlled as a mechanism for controllably establishing a threshold voltage for the field effect transistor.
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Citations
9 Claims
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1. A method of making a field effect transistor including:
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depositing on a semi-insulating substrate a semiconductor layer of a first conductivity type; forming a channel of a second conductivity type opposite from said first conductivity type in said substrate, thereby forming a pn junction with said layer; disposing a metallic gate electrode on said layer opposite said channel; and forming spaced apart source and drain regions of said second conductivity type in said layer, extending into said substrate, and contacting said channel, said source and drain regions lying on opposite sides of said gate electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification