Method of making a extended integration semiconductor structure

• US 5,192,716 A
• Filed: 07/24/1991
• Issued: 03/09/1993
• Est. Priority Date: 01/25/1989
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia, Inc.)
• Original Assignee: Polylithics, Inc.
• Inventors: Jacobs, Scott L.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US07/735,340
• Time in Patent Office: 594 Days
• Field of Search: 437/209, 437/211, 437/205, 437/213, 437/215, 437/221, 174/52.1, 174/52.5, 174/52.4, 361/400, 361/401, 29/831, 29/832, 29/854
• US Class Current: 29/832
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A low cost, lightweight, fast, dense and reliable extended integration semiconductor structure is provided by forming a thin film multilayer wiring decal on a support substrate and aligning and attaching one or more integrated chips to the decal. A support ring is attached to the decal surrounding the aligned and attached integrated substrate, and the support substrate is removed. Reach-through vias connect the decal wiring to the chips.

Claims

1. A method of forming an extended integration structure comprising the steps of:

forming on a support substrate;

a thin film decal having at least one wiring layer therein;

aligning at least one integrated circuit chip to said thin film decal;

attaching the at least one integrated circuit chip to said thin film decal;

mounting a support ring on said thin film decal, surrounding said at least one integrated circuit chip;

removing said support substrate; and

electrically connecting said at least one wiring layer to said at least one integrated circuit chip.

2. The method of claim 1 wherein said forming step comprises the steps of:

providing a support substrate;

forming a first insulating layer on said support substrate;

forming a first wiring layer on said first support substrate; and

forming a second insulating layer on said first wiring layer.

3. The method of claim 1 wherein said forming step comprises the step of:

forming a plurality of wiring layers on said support substrate, said wiring layers being insulated from one another.

4. The method of claim 1 wherein said forming step comprises the steps of:

providing a transparent support substrate;

forming a transparent insulating layer on said support substrate;

forming a wiring layer on said transparent insulating layer;

passing radiation through said support substrate, said transparent insulating layer and said wiring layer; and

comparing the pattern of radiation which passes through said support substrate, said insulating layer and said wiring layer, to an expected pattern of radiation, to thereby test said wiring layer.

5. The method of claim 4 wherein the steps of forming a transparent insulating layer, forming a wiring layer, passing radiation and comparing the pattern are repeatedly performed to a plurality of insulated wiring layers.

6. The method of claim 1 wherein said forming step comprises the steps of:

forming a first wiring layer on said support substrate;

forming a second wiring layer on a second substrate;

attaching said second wiring layer to said first wiring layer; and

removing said second substrate;

7. The method of claim 6 wherein the steps of forming a first wiring layer on said support substrate is followed by the step of optically testing said first wiring layer, and wherein the step of forming a second wiring layer on a second substrate is followed by the step of optically testing said second wiring layer.

8. The method of claim 6 wherein said removing said second substrate step is followed by the step of:

selectively connecting said first and second wiring layers.

9. The method of claim 8 wherein said selectively connecting step comprises the step of forming a plurality of reach-through-vias between said first and second wiring layers.

10. The method of claim 1 wherein said support substrate is transparent and wherein said aligning step comprises the steps of:

placing said support substrate over said at least one integrated circuit chip with said thin film decal adjacent said integrated circuit chip, and aligning said decal to said at least one chip through said substrate.

11. The method of claim 10 wherein said aligning step comprises the step of visually aligning said decal to said at least one chip through said transparent substrate.

12. The method of claim 1 wherein said aligning step is preceded by the step of:

providing a surface attachment layer on said at least one integrated circuit chip.

13. The method of claim 12 wherein the step of providing a surface attachment layer comprises the steps of:

providing an adhesion promotor on the surface of said at lest one integrated circuit chip; and

providing a thin layer of permanent dielectric on said adhesion promotor.

14. The method of claim 1 wherein said removing step comprises the step of:

destroying the bond between said thin film decal and said support substrate.

15. The method of claim 1 wherein the removing step is preceded by the step of curing said thin film decal.

16. The method of claim 1 wherein said electrically connecting step comprises the step of forming a plurality of reach-through vias between said at least one wiring layer and said at least one integrated circuit chip.

17. The method of claim 16 wherein said reach-through-vias are formed by a liftoff technique.

18. The method of claim 16 wherein said reach-through-vias are formed by a lost wax technique.

19. The method of claim 2 wherein said step of forming a second insulating layer is followed by the step of partially etching said second insulating layer to undercut a portion of said first wiring layer and provide a mechanical joint for a next insulating layer.

20. The method of claim 2 wherein said step of forming a first insulating layer is followed by the step of curing said first insulating layer.

21. The method of claim 4 wherein said comparing step is followed by the step of:

repairing said wiring layer if the pattern of radiation is not the same as the expected pattern of radiation.

22. The method of claim 1 further comprising the steps of:

testing said at least one integrated circuit chip; and

removing said at least one integrated circuit chip from said decal if said at least one integrated circuit chip is defective.

23. The method of claim 1 further comprising the step of:

forming additional wiring layers on said thin film decal.

24. The method of claim 1 further comprising the step of:

forming input/output connectors for a next level of packaging on said thin film decal.

25. The method of claim 24 wherein said step of forming input/output connectors comprises the step of forming input/output connectors for tab automated bonding to a next level of packaging.

26. The method of claim 1 further comprising the step of mounting said extended integration structure on a second extended integration semiconductor structure.

27. A method of forming an extended integration semiconductor structure comprising the steps of:

forming on a support substrate, a thin film decal having at least one wiring layer therein;

aligning an integrated circuit chip to said thin film decal;

attaching the aligned integrated circuit chip to said thin film decal;

repeating said aligning and attaching steps to align and attach a plurality of integrated circuit chips to said thin film decal;

mounting a support ring on said thin film decal, surrounding said plurality of integrated circuit chips;

removing said support substrate; and

selectively electrically connecting said at least one wiring layer to said plurality of integrated circuit chips.

28. The method of claim 27 wherein said forming step comprises the steps of:

providing a support substrate;

forming a first insulating layer on said support substrate;

forming a first wiring layer on said first support substrate; and

forming a second insulating layer on said first wiring layer.

29. The method of claim 27 wherein said forming step comprises the step of:

forming a plurality of wiring layers on said support substrate, said wiring layers being insulated form one another.

30. The method of claim 27 wherein said forming step comprises the steps of:

providing a transparent support substrate;

forming a transparent insulating layer on said support substrate;

forming a wiring layer on said transparent insulating layer;

passing radiation through said support substrate, said first insulating layer and said first wiring layer; and

comparing the pattern of radiation which passes through said support substrate, said insulating layer and said wiring layer, to an expected pattern of radiation, to thereby test the wiring layer.

31. The method of claim 30 wherein the steps of forming a transparent insulating layer, forming a wiring layer, passing radiation and comparing the pattern are repeatedly performed to form a plurality of insulated wiring layers.

32. The method of claim 27 wherein said forming step comprises the steps of:

forming a first wiring layer on said support substrate;

forming a second wiring layer on a second substrate;

attaching said second wiring layer to said first wiring layer; and

removing said second substrate.

33. The method of claim 32 wherein the step of forming a first wiring layer on said support substrate is followed by the step of optically testing said first wiring layer, and wherein the step of forming a second wiring layer on a second substrate is followed by the step of optically testing said second wiring layer.

34. The method of claim 32 wherein said removing said second substrate step is followed by the step of:

selectively connecting said first and second wiring layers.

35. The method of claim 34 wherein said selectively connecting step comprises the step of forming a plurality of reach-through-vias between said first and second wiring layers.

36. The method of claim 27 wherein said support substrate is transparent and wherein said aligning step comprises the steps of:

placing said support substrate over said integrated circuit chip with said thin film decal adjacent said integrated circuit chip, and aligning said decal to said chip through said substrate.

37. The method of claim 27 wherein said aligning step comprises the step of visually aligning said decal to said chip through said transparent substrate.

38. The method of claim 27 wherein said aligning step is preceded by the step of:

providing a surface attachment layer on said chip.

39. The method of claim 38 wherein the step of providing a surface attachment layer comprises the steps of:

providing an adhesion promotor on the surface of said chip; and

providing a thin layer of permanent dielectric on said adhesion promotor.

40. The method of claim 27 wherein said removing step comprises the step of:

destroying the bond between said thin film decal and said support substrate.

41. The method of claim 27 wherein the removing step is preceded by the step of curing said thin film decal.

42. The method of claim 27 wherein said electrically connecting step comprises the step of forming a plurality of reach-through vias between said at least one wiring layer and said plurality of integrated circuit chips.

43. The method of claim 42 wherein said reach-through-vias are formed by a liftoff technique.

44. The method of claim 42 wherein said reach-through-vias are formed by a lost wax technique.

45. The method of claim 28 wherein said step of forming a second insulating layer is followed by the step of partially etching said second insulating layer to undercut a portion of said first wiring layer and provide a mechanical joint for a next insulating layer.

46. The method of claim 28 wherein said step of forming a first insulating layer is followed by the step of curing said first insulating layer.

47. The method of claim 30 wherein said comparing step is followed by the step of:

repairing said wiring layer if the pattern of radiation is not the same as the expected pattern of radiation.

48. The method of claim 27 further comprising the steps of:

testing said plurality of integrated circuit chips; and

removing at least one of said plurality of integrated circuit chips form said decal if said at least one chip is defective.

49. The method of claim 27 further comprising the step of:

forming additional wiring layers on said thin film decal.

50. The method of claim 27 further comprising the step of:

forming input/output connectors for a next level of packaging on said thin film decal.

51. The method of claim 50 wherein said step of forming input/output connectors comprises the step of forming input/output connectors for tab automated bonding to a next level of packaging.

52. The method of claim 27 further comprising the step of mounting said extended integration structure on a second extended integration semiconductor structure.

53. A method of forming a plurality of extended integration structures, comprising the steps of:

forming on a support substrate, a thin film decal having at least one wiring layer therein;

aligning a plurality of integrated circuit chips to said thin film decal;

attaching said plurality of aligned integrated circuit chips to said thin film decal;

mounting a plurality of support rings on said thin film decal, each of said support rings surrounding said at least one of said plurality of integrated circuit chips;

removing said support substrate; and

selectively electrically connecting said at least one wiring layer to said plurality of integrated circuit chips.

54. The method of claim 53 wherein said forming step comprises the steps of:

providing a support substrate;

forming a first insulating layer on said support substrate;

forming a first wiring layer on said first support substrate; and

forming a second insulating layer on said first wiring layer.

55. The method of claim 53 wherein said forming step comprises the step of:

forming a plurality of wiring layers on said support substrate, said wiring layers being insulated from one another.

56. The method of claim 53 wherein said forming step comprises the steps of:

providing a transparent support substrate;

forming a transparent insulating layer on said support substrate;

forming a wiring layer on said transparent insulating layer;

passing radiation through said support substrate, said first insulating layer and said first wiring layer; and

comparing the pattern of radiation which passes through said support substrate, said insulating layer and said wiring layer, to an expected pattern of radiation, to thereby test the wiring layer.

57. The method of claim 56 wherein the steps of forming a transparent insulating layer, forming a wiring layer, passing radiation and comparing the pattern are repeatedly performed to form a plurality of insulated wiring layers.

58. The method of claim 53 wherein said forming step comprises the steps of:

forming a first wiring layer on said support substrate;

forming a second wiring layer on a second substrate;

attaching said second wiring layer to said first wiring layer; and

removing said second substrate.

59. The method of claim 58 wherein the step of forming a first wiring layer on said support substrate is followed by the step of optically testing said first wiring layer, and wherein the step of forming a second wiring layer on a second substrate is followed by the step of optically testing said second wiring layer.

60. The method of claim 58 wherein said removing said second substrate step is followed by the step of:

selectively connecting said first and second wiring layers.

61. The method of claim 60 wherein said selectively connecting step comprises the step of forming a plurality of reach-through-vias between said first and second wiring layers.

62. The method of claim 53 wherein said support substrate is transparent and wherein said aligning step comprises the steps of:

placing said support substrate over one of said plurality of integrated circuit chips with said thin film decal adjacent said one of said plurality of integrated circuit chips, and aligning said decal to said one of said plurality of chips through said substrate.

63. The method of claim 62 wherein said aligning step comprises the step of visually aligning said decal to said one of said plurality of chips through said transparent substrate.

64. The method of claim 53 wherein said aligning step is preceded by the step of:

providing a surface attachment layer on said at least one integrated circuit chip.

65. The method of claim 64 where the step of providing a surface attachment layer comprises the steps of:

providing an adhesion promotor on the surface of said at least one integrated circuit chip; and

providing a thin layer of permanent dielectric on said adhesion promotor.

66. The method of claim 53 wherein said removing step comprises the step of:

destroying the bond between said thin film decal and said support substrate.

67. The method of claim 53 wherein the removing step is preceded by the step of curing said thin film decal.

68. The method of claim 53 wherein said selectively electrically connecting step comprises the step of forming a plurality of reach-through vias between said at least one wiring layer and said plurality of integrated circuit chips.

69. The method of claim 68 wherein said reach-through-vias are formed by a liftoff technique.

70. The method of claim 68 wherein said reach-through-vias are formed by a lost wax technique.

71. The method of claim 53 wherein said aligning and attaching steps are successively performed on each one of said plurality of integrated circuit chips.

72. The method of claim 53 further comprising the step of cutting said thin film decal around each of said plurality of support rings to provide a plurality of extended integration structures.

73. The method of claim 54 wherein said step of forming a second insulating layer is followed by the step of partially etching said second insulating layer to undercut a portion of said first wiring layer and provide a mechanical joint for a next insulating layer.

74. The method of claim 54 wherein said step of forming a first insulating layer is followed by the step of curing said first insulating layer.

75. The method of claim 56 wherein said comparing step is followed by the step of:

repairing said wiring layer if the pattern of radiation is not the same as the expected pattern of radiation.

76. The method of claim 53 further comprising the steps of:

testing said plurality of integrated circuit chips; and

removing at least one of said plurality of integrated circuit chips from said decal if said at least one chip is defective.

77. The method of claim 53 further comprising the step of:

forming additional wiring layers on said thin film decal.

78. The method of claim 53 further comprising the step of:

forming input/output connectors for a next level of packaging on said thin film decal.

79. The method of claim 78 wherein said step of forming input/output connectors comprises the step of forming input/output connectors for tab automated bonding to a next level of packaging.

80. The method of claim 53 further comprising the step of mounting said extended integration structure on a second extended integration semiconductor structure.

81. A method of forming an extended integration wafer-scale integration structure comprising the steps of:

forming on a support substrate, a thin film decal having at least one wiring layer therein;

aligning at lest one integrated circuit chip to said thin film decal;

attaching the at least one integrated circuit chip to said thin film decal;

aligning and attaching a wafer to said thin film decal, surrounding said at least one integrated circuit chip;

removing said support substrate; and

electrically connecting said at least one wiring layer to said at least one integrated circuit chip and said wafer.

82. The method of claim 81 wherein said forming step comprises the steps of:

providing a support substrate;

forming a first insulating layer on said support substrate;

forming a first wiring layer on said first support substrate; and

forming a second insulating layer on said first wiring layer.

83. The method of claim 81 wherein said forming step comprises the steps of:

forming a plurality of wiring layers on said support substrate, said wiring layers being insulated from one another.

84. The method of claim 81 wherein said forming step comprises the steps of:

providing a transparent support substrate;

forming a transparent insulating layer on said support substrate;

forming a wiring layer on said transparent insulating layer;

passing radiation through said support substrate, said transparent insulating layer and said wiring layer; and

comparing the pattern of radiation which passes through said support substrate, said insulating layer and said wiring layer, to an expected pattern of radiation, to thereby test said wiring layer.

85. The method of claim 84 wherein the steps of forming a transparent insulating layer, forming a wiring layer, passing radiation and comparing the pattern are repeatedly performed to form a plurality of insulated wiring layers.

86. The method of claim 84 wherein said forming step comprises the steps of:

forming a first wiring layer on said support substrate;

forming a second wiring layer on a second substrate;

attaching said second wiring layer to said first wiring layer; and

removing said second substrate.

87. The method of claim 86 wherein the step of forming a first wiring layer on said support substrate is followed by the step of optically testing said first wiring layer, and wherein the step of forming a second wiring layer on a second substrate is followed by the step of optically testing said second wiring layer.

88. The method of claim 86 wherein said removing said second substrate step is followed by the step of:

selectively connecting said first and second wiring layers.

89. The method of claim 88 wherein said selectively connecting step comprises the step of forming a plurality of reach-through-vias between said first and second wiring layers.

90. The method of claim 81 wherein said forming step comprises the steps of:

forming a first wiring layer on said support substrate;

forming a second wiring layer on a second substrate;

attaching said second wiring layer to said first wiring layer; and

removing said second substrate.

91. The method of claim 90 wherein the step of forming a first wiring layer or said support substrate is followed by the step o optically testing said first wiring layer, and wherein the step of forming a second wiring layer on a second substrate is followed by the step of optically testing said second wiring layer.

92. The method of claim 81 wherein said aligning step is preceded by the step of:

providing a surface attachment layer on said at least one integrated circuit chip.

93. The method of claim 92 where the step of providing a surface attachment layer comprises the steps of:

providing an adhesion promotor on the surface of said at least one integrated circuit chip; and

providing a thin layer of permanent dielectric on said adhesion promotor.

94. The method of claim 81 wherein said removing said second substrate step is followed by the step of:

selectively connecting said first and second wiring layers.

95. The method of claim 81 wherein said selectively connecting step comprises the step of forming a plurality of reach-through-vias between said first and second wiring layers.

96. The method of claim 81 wherein said support substrate is transparent and wherein said aligning step comprises the steps of:

placing said support substrate over said at least one integrated circuit chip with said thin film decal adjacent said integrated circuit chip, and aligning said decal to said at least one chip through said substrate.

97. The method of claim 96 wherein said reach-through-vias are formed by a liftoff technique.

98. The method of claim 96 wherein said reach-through-vias are formed by a lost wax technique.

99. The method of claim 82 wherein said aligning step comprises the step of visually aligning said decal to said at least one chip through said transparent substrate.

100. The method of claim 82 wherein said step of forming a first insulating layer is followed by the step of curing said first insulating layer.

101. The method of claim 82 wherein said comparing step is followed by the step of:

repairing said wiring layer if the pattern of radiation is not the same as the expected pattern of radiation.

102. The method of claim 81 further comprising the steps of:

testing said at least one integrated circuit chip; and

removing said at least one integrated circuit chip; and

removing said at least one integrated circuit chip from said decal if said at least one integrated circuit chip is defective.

103. The method of claim 81 further comprising the step of:

forming additional wiring layers on said thin film decal.

104. The method of claim 81 further comprising the step of:

forming input/output connectors for a next level of packaging on said thin film decal.

105. The method of claim 104 wherein said step of forming input/output connectors comprises the step of forming input/output connectors for tab automated bonding to a next level of packaging.

106. The method of claim 104 further comprising the step of mounting said extended integration structure on a second extended integration semiconductor structure.