Digital data transmission system having error detecting and correcting function

• US 5,192,949 A
• Filed: 08/30/1990
• Issued: 03/09/1993
• Est. Priority Date: 08/31/1989
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Aoki, Shinji, Suzuki, Hideto, Kurose, Yoshikazu
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US07/575,377
• Time in Patent Office: 922 Days
• Field of Search: 341/68, 341/58, 341/50, 341/69-74, 371/37.4
• US Class Current: 341/68
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: G11B 20/1809 by interleaving
• CPC Class Codes: G11B 2020/1434 8 to 9 modulation
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/251 with block coding
• CPC Class Codes: H03M 13/253 with concatenated codes
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2909 Product codes
• CPC Class Codes: H03M 13/293 with erasure setting
• CPC Class Codes: H03M 13/3738 with judging correct decoding

Abstract

In an information data recording and reproducing device which can record and reproduce input information data accurately, an error correction code of the product sign format is added to the input information data to form coded data. The coded data are then NRZI converted and recorded onto a recording medium together with identification data of a predetermined data pattern. Error detecting and correcting are performed on data reproduced from the recording medium so as to obtain the data recorded on the recording medium. The device comprises an NRZI converting circuit for outputting the identification data as they are, that is, without NRZI conversion, and for NRZI converting the coded data using the last bit of the identification data as an initial value, and a memory controlling circuit for controlling writing and reading of a memory, which is provided to convert the reproduction data from a series of inner codes into another series of outer codes, so that write address information for the memory which is obtained from the reproduction data may be compensated for when it is not obtained properly and outer code error detection and correction may be readily executed.

Claims

1. In an information transmission system for coding n-bit information data in the form of an NRZL code into m-bit coded data such that each of said information data corresponds to only one of said coded data which are all different from one another, n being greater than 2 and m being greater than n, NRZI converting said m-bit coded data such that m-bit coded data having a codeword digital sum (CDS) which does not have the same polarity as a digital sum variation (DSV) of previously NRZI converted m-bit coded data is selected as a next NRZI conversion input to limit the DSV of the NRZI converted signal, and transmitting the thus NRZI converted coded data, the combination of:

first controlling means for generating a control signal to control NRZI conversion of said m-bit coded data and for generating a mode signal;

code generating means for generating identification data having a predetermined data pattern corresponding to said n-bit information data and for outputting said identification data and said m-bit coded data obtained by coding of said n-bit information data in response to said mode signal and a coding control signal;

CDS generating means for generating a CDS corresponding to said identification data and m-bit coded data output by said code generating means in response to said mode signal and the coding control signal;

NRZI converting means responsive to said control signal from said first controlling means for outputting the identification data obtained from said code generating means as they are without NRZI converting the same and for executing NRZI conversion of said m-bit coded data outputted from said code generating means using an initial value determined by a conversion initial value signal;

latching means for latching the last bit of the identification data outputted from said NRZI converting means and providing the latched bit as said conversion initial value signal;

DSV detecting means for detecting a current DSV corresponding to an output signal of said NRZI converting means in response to said conversion initial value signal and a DSV immediately preceding said current DSV; and

second controlling means for generating said coding control signal in response to said control signal from said first controlling means, said identification data and m-bit coded data output from said CDS generating means, said conversion initial value signal and the detected current DSV from said DSV detecting means to limit the DSV of the output signal of said NRZI converting means.

2. An information transmission system according to claim 1, wherein said code generating means includes a ROM in which said m-bit boded data and identification data are stored and from which the coded data and identification data are outputted when respective addresses are designated by said input information data, said mode signal and said coding control signal.

3. An information transmission system according to claim 1, wherein said CDS generating means includes a ROM in which said m-bit coded data and a CDS corresponding to said identification data are stored and from which the CDS is outputted when a respective address is designated by said input information data, said mode signal and said coding control signal.

4. An information transmission system according to claim 1, wherein said NRZI converting means includes means for NRZI converting said m-bit coded data in a parallel state, and parallel to serial converting means for converting an output of said means for NRZI converting into a serial signal.

5. An information transmission system according to claim 4, wherein said means for NRZI converting includes a ROM in which are stored NRZI converted data corresponding to said m-bit coded data and from which NRZI converted data is outputted when an respective address is designated by said m-bit- coded data from said code converting means and said conversion initial value signal, and the output of said ROM is converted into a serial signal by said parallel to serial converting means.

6. An information transmission system according to claim 4, wherein said means for NRZI converting includes m- exclusive OR circuits and a D flipflop, each of the m bits of said m-bit coded data being inputted to one of a pair of input terminals of a respective one of said exclusive OR circuits, an output signal of each one of said exclusive OR circuits being inputted to the other input terminal of a next one of said exclusive OR circuits except that the one of said exclusive OR circuits to which the least significant bit of said m-bit coded data is inputted has, as its input to the other input terminal thereof an output signal of that one of said exclusive OR circuits to which the most significant bit of said m-bit coded data is supplied through said D flipflop, whereby a signal in a parallel state obtained by NRZI conversion of the m-bit coded data is outputted from said m exclusive OR circuits and then is converted into a serial state by said parallel to serial converting means.

7. An information transmission system according to claim 1, wherein said DSV detecting means includes calculating means for adding or subtracting an output of said CDS generating means to or from, respectively, the immediately preceding DSV of said NRZI converted m-bit coded signal in response to the conversion initial value signal, and storage means for temporarily storing an output of said calculating means therein.

8. An information transmission system according to claim 7, wherein said CDS and said DSV are of opposite polarity and only the most significant bit of an output of said calculating means of said DSV detecting means is used as DSV data.

9. An information transmission system for converting coded data in the form of an NRZL code into an NRZI code and transmitting the NRZI code together with identification data included in a predetermined data pattern, comprising:

NRZI converting means for NRZI converting said coded data but outputting the identification data without NRZI conversion; and

latch means for latching the last bit of said identification data of an output of said NRZI converting means, and said NRZI converting means NRZI converting said coded data using output data of said latch means as an initial value.

10. An information transmission system according to claim 9, wherein said coded data inputted to said NRZI converting means has an m-bit parallel arrangement, and said NRZI converting means NRZI converts said coded data of m-bit parallel arrangement in a parallel state.

11. An information transmission system according to claim 10, wherein said NRZI converting means includes a ROM from which a signal of parallel arrangement obtained by NRZI conversion of said coded data is outputted when an address is designated by said coded data and output data of said latch means.

12. An information transmission system according to claim 10, wherein said NRZI converting means includes a number of exclusive OR circuits equal to the bit number m of said m-bit coded data and a D flipflop, each of the m bits of said m-bit code data being inputted to one of a pair of input terminals of a respective one of said exclusive OR circuits while an output signal of each adjacent one of said exclusive OR circuits is inputted to the other input terminal of each of said exclusive OR circuits except that the one of said exclusive OR circuits to which the least significant bit of said m-bit coded data are inputted has, as it input to the other input terminal, an output signal of that one of said exclusive OR circuits to which the most significant bit of said m-bit coded data is inputted by way of said D flipflop, whereby a signal in a parallel state obtained by NRZI conversion of the m-bit coded data is outputted from said m exclusive OR circuits.

13. An information transmission system according to claim 10, wherein said NRZI converting means includes parallel to serial converting means for converting NRZI converted data of a parallel arrangement into data of a serial arrangement.

14. An information recording device for converting coded data in the form of an NRZL code into NRZI coded data and recording the NRZI coded data together with identification data included in a predetermined data pattern, comprising:

NRZI converting means for NRZI converting said coded data while outputting the identification data without NRZI conversion thereof;

latch means for latching a last bit of said identification data in an output of said NRZI converting means;

said NRZI converting means NRZI converting said coded data using output data of said latch means as an initial value; and

means for recording an output signal of said NRZI converting means on a record medium.

15. An information recording device according to claim 14, wherein said coded data inputted to said NRZI converting means has an m-bit parallel arrangement, and said NRZI converting means NRZI converts the coded data of said m-bit parallel arrangement while in a parallel state.

16. An information recording device according to claim 15, wherein said NRZI converting means includes a ROM from which a signal having a parallel arrangement and which is obtained by NRZI conversion of said coded data is outputted when an address thereof is designated by said coded data and output data from said latch means.

17. An information recording device according to claim 15, wherein said NRZI converting means includes a number of exclusive OR circuits equal to the bit number m of said m-bit coded data and a D flipflop, each of the m bits of said m-bit coded data being inputted to one of a pair of input terminals of a respective one of said exclusive OR circuits while an output signal from an adjacent one of said exclusive OR circuits, to which a lower adjacent bit of said m-bit coded data is inputted, is supplied to the other input terminal of each of said exclusive OR circuits, except that the one of said exclusive OR circuits to which the least significant bit of said m-bit coded data is supplied, has, as its input to the other input terminal, an output signal from that one of said exclusive OR circuits to which the most significant bit of said m-bit is inputted, supplied by way of said D flipflop, whereby a signal in a parallel state obtained by NRZI conversion of said m-bit coded data is outputted from said m exclusive OR circuits.

18. An information recording device according to claim 15, wherein said NRZI converting means includes parallel to serial converting means for converting NRZI converted data having a parallel arrangement into data having a serial arrangement.

19. An information data recording and reproducing device for adding an error correction code of the product sign format to input information data to form coded data, NRZI converting the coded data, recording the NRZI converted coded data together with predetermined data including identification data on a record medium, and performing error detection and correction of reproduction data obtained from such record medium to reproduce data recorded on the record medium, comprising:

NRZI converting means for outputting the identification data without NRZI conversion thereof while NRZI converting the coded data, said NRZI converting means further including a latch means for latching the last bit of the identification data outputted from said NRZI converting means said NRZI converting means using output data of said latch means as an initial value in said NRZI converting of said coded data;

inner code error detecting and correcting means for detecting an inner code error of said transmission data, correcting the thus detected inner code error and outputting inner code correction data in a predetermined block data unit;

memory means for storing said inner code correction data therein;

counting means for counting said inner code correction data for each said block of data as a unit;

identification data detecting means for detecting identification data of each said block of data of the inner code correction data which is free of error or which has been corrected to eliminate error;

offset detecting means for detecting an offset amount between output data of said counting means and output data of said identification data detecting means and providing corresponding offset data;

adding means for adding the output data of said identification data detecting means and output data of said offset detecting means and providing an added output which presets said counting means;

monitoring means for monitoring continuity of said block data on the basis of output data of said counting means and output data of said identification data detecting means as well as an error flag generated by said inner code error detecting and correcting means, and for judging from said monitoring whether or not the block data are correct block data and providing a corresponding selecting signal;

data selecting means for selecting either the output data of said counting means or the output data of said identification data detecting means as an output signal in response to said selecting signal of said monitoring means;

address generating means for generating address data identifying addresses at which said inner code correction data are to be written in said memory means in response to the output data from said data selecting means; and

outer code error detecting and correcting means for reading out data stored in said memory means in accordance with a series of outer codes in accordance with said offset data from said offset detecting means, detecting an outer code error of the data thus read out and correcting the outer code error thus detected.