Active matrix liquid crystal display system using complementary thin film transistors

• US 5,193,018 A
• Filed: 10/28/1991
• Issued: 03/09/1993
• Est. Priority Date: 10/28/1991
• Status: Expired due to Term

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wu, Biing-Seng
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Mai, Huy K.
• Application Number:
  US07/783,575
• Time in Patent Office: 498 Days
• Field of Search: 359/54, 359/58, 359/59, 359/68, 340/784
• US Class Current: 349/43
• CPC Class Codes: G02F 1/13 based on liquid crystals, e.g. single liquid crystal display cells

Abstract

A matrix display system includes an active matrix display device having an array of liquid crystal picture elements (pixel) with associated switches using thin film transistors (TFT). The pixels are arranged in groups, each having two pixels and switched by two complementary TFTs. The n-channel TFTs are switched on by a positive pulse and the p-channel TFTs are switched on by a negative pulse. The two switching signals are alternately fed from a row conductor which feeds both the n-channel TFTs and the p-channel TFTs on the same row. Each group of the two TFTs are addressed via the same row conductor and the same column conductor, which carries the data signal. In this way, either the number of row conductors are reduced by one half or the number of column conductors are reduced by one half.

Claims

1. A thin film transistor active matrix display system comprising:

a plurality of liquid crystal display picture elements arranged in rows and columns and divided into groups;

each said group of said pixels containing two said pixels,

a plurality of scan lines;

a plurality of data lines;

each said group addressed by the same scan line and the same data line,

two switches for connecting said pixels of one of said group with said data line, each one of said switches connected only to one of said pixels,

a n-channel thin film transistor (TFT) serving as one of said switches,

a p-channel TFT serving as another one of said switches,

said two TFTs having common gates connected to said scan line, common drains connected to said data line, and separate sources connected two said pixels in the same group.

2. A thin film transistor active matrix display system according to claim 1, wherein the threshold voltages of the n-channel TFTs and the p-channel TFTs serving as said switches are designed to be higher than the maximum voltage of said data signal.

3. A thin-film transistor active matrix display system according to claim 1, wherein the p-channel TFT and the n-channel TFT in each said group are located on different sides of said scan line, resulting in n/2 total said switching signal conductors, each said scan line connected to m number of said groups, where n is the total number of rows of pixels in said matrix.

4. A thin-film transistor active matrix display system according to claim 3, wherein the switching signal for the scan line comprises a switching waveform which has a positive voltage pulse width which all the pixels connected to the n-channel TFTs of one said row are energized, and a negative voltage pulse width which all the pixels connected to the p-channel TFTs of one said row are energized;

and the corresponding data line signals are supplied in synchronism with in said switching waveform.

5. A thin-film transistor active matrix display system according to claim 4, wherein the pulse width of the positive voltage and the pulse width of the negative voltage can be equal or different, and are dependent on the geometries and mobilities of the n-channel TFTs and the p-channel TFTs.

6. A thin film transistor active matrix display system according to claim 3, wherein the duration of the positive pulse corresponding to the duration of the scan signal applied to n-channel TFTs in a said scan line is equal to the line scanning period of television display, whereas the duration of the negative pulse corresponding to the duration of the scan signal applied to p-channel TFTs in said scan line is equal to the line scanning period of a television display.

7. A thin-filn transistor active matrix display system according to claim 3, wherein the n-channel thin-film transistor of each said group is located above the row conductor, and the p-channel thin-film transistor of each said group is located below the row conductor.

8. A thin-film transistor active matrix display system according to claim 3, wherein the n-channel thin-film transistors are located below the row conductor, and the p-channel thin-film transistors are located above the row conductor.

9. A thin-film transistor active matrix display system according to claim 3, wherein the n-channel thin-film transistors and the p-channel thin-film transistors are alternately or disorderly placed with respect to the row conductor.

10. A thin-film trnasistor active matrix display system according to claim 1, wherein the p-channel TFT and the n-channel TFT in each group are located on different sides of said data line, resulting in m/2 total said data lines, each connected to n number of said groups, where m is the total number of columns of pixels in said matrix.

11. A matrix display system according to claim 4, wherein during the positive switching pulse on said scan line, every two energized pixels on an energized scan line are separated by an unenergized pixel;

and during the negative switching pulse on said scan line, every two energized pixels on the energized scan line are also separated by an unenergized pixel.

12. A thin-film trnasistor active matrix display system according to claim 10, wherein the n-channel thin-film transistor of each said group is located on the left-hand side of the column conductor, and the p-channel thin-film transistor of each said group is located on the right-hand side of the column conductor.

13. A thin-film transistor active matrix display system according to claim 10, wherein the n-channel thin-film transistor of each said group is located on the right-hand side of the column conductor, and the p-channel thin-film transistor of each said group is located on the left-hand side of the column conductor.

14. A thin-film transistor active matrix display system according to claim 10, wherein the n-channel thin-film transistors and the p-channel thin-film transistors are alternately or disorderly located with respect to the column conductor.

15. A thin-film trnasistor active matrix display system according to claim 1, wherein the TFTs are made of polycrystalline silicon or amorphous silicon or other semionductor materials.

16. A thin-film transistor active matrix display system according to claim 1, wherein every three successive pixels are arranged to display three primary colors.