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Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are synchronized upon each voted access to two memory modules

  • US 5,193,175 A
  • Filed: 03/06/1991
  • Issued: 03/09/1993
  • Est. Priority Date: 12/09/1988
  • Status: Expired due to Term
First Claim
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1. A fault-tolerant computer system, comprising:

  • first, second and third CPUs, each executing a same given instruction stream;

    first and second memory modules each storing the same data in response to execution by said CPUs of said instruction stream;

    busses coupling each of the first, second and third CPUs individually to each of said first and second memory modules for said first, second and third CPUs to access said first and second memory modules separately or in duplicate, said first, second and third CPUs each executing said same given instruction stream, wherein each said CPU execution is clocked independently such that at least one earlier CPU among said CPUs asynchronously accesses said first and second memory modules after said earlier CPU executes plural consecutive instructions asynchronously and prior to a last CPU among said CPUs asynchronously accessing said first and second memory modules, and said earlier and last CPUs accessing to said memory modules being detected by said memory modules;

    synchronizing means for synchronizing said first, second and third CPUs, said synchronizing means enabling said first and second memory modules to detect said asynchronous access by said earlier and last CPUs to said first and second memory modules, said synchronizing means stalling any CPUs for which the access occurs earlier to wait until the last one of said CPUs executes said access, and said synchronizing means thereafter allowing the access to occur asynchronously;

    a first input/output bus coupled to said first memory module and a second input/output bus coupled to said second memory modules; and

    a first input/output processor coupled to both said first and second input/output busses, and a second input/output processor coupled to both said first and second input/output busses.

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