Circuit for interfacing between a microprocessor and a plurality of power stages, particularly for controlling electro-injectors

• US 5,195,011 A
• Filed: 11/07/1990
• Issued: 03/16/1993
• Est. Priority Date: 11/07/1989
• Status: Expired due to Fees

• Current Assignee: Marelli Autronica SPA
• Original Assignee: Marelli Autronica SPA
• Inventors: Morello, Gianluigi, LeGrand, Yves, Giorgetta, Valerio, Salerno, Franco
• Primary Examiner(s): DEBOER, TODD
• Application Number:
  US07/609,846
• Time in Patent Office: 860 Days
• Field of Search: 361/42, 361/86, 361/87, 361/111, 361/94, 361/93, 361/154, 123/480, 123/479, 123/490
• US Class Current: 361/87
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches

Abstract

The interface circuit described comprises a plurality of control stages, each of which can detect and indicate a short-circuit in the corresponding load or the associated power transistor.

In particular, the interface circuit is arranged to disable a transistor permanently when short-circuits occur repeatedly in the load in order to prevent damage to the transistor.

Claims

1. A circuit for interfacing between a microprocessor and a plurality of transistors, particularly MOSFET power transistors for driving a corresponding plurality of loads, particularly electrical injectors, each of which is connected to the drain-source path of one of the transistors through a feedback terminal and between the positive and negative terminals of a direct-current voltage supply;

the circuit including a plurality of control stages each of which is associated with one of the transistors and comprises

a first input terminal for receiving a control logic signal,

a first output terminal for connection to the gate of the associated power transistor,

a driver circuit, connected between the first input terminal and the first output terminal and adapted to make the transistor conductive when an enabling signal is present at its enabling input and the control logic signal is applied to the first input terminal, and

a diagnostic logic circuit, connected to said first terminal and said feedback terminal and to the enabling input of the driver circuit the diagnostic circuit being arranged

to detect a short-circuit condition between the drain of the transistor and the positive terminal of the voltage supply;

to apply a disabling signal to the control circuit for a period of temporary disablement when a first short-circuit condition occurs between the drain of the transistor and the positive terminal of the supply;

to output a first breakdown signal and to apply a permanent disablement signal to the control circuit when a short-circuit condition is again detected between the drain of the transistor and the positive terminal of the supply after the temporary disablement period has elapsed.

3. A circuit according to claim 1, wherein in each control stage the diagnostic logic circuit is also arranged

to detect a short-circuit condition between the drain of the associated power transistor and the negative terminal of the supply and/or the disconnection of the load from the associated transistor on the basis of a comparison of the signals present at the first and second inputs and

to output a corresponding second breakdown signal.

4. A circuit according to claim 3, including a single diagnosis-indication logic circuit connected to the outputs of the diagnostic circuits of the individual control stages;

the diagnosis-indication circuit being arranged to output digital information signals for identifying the stage corresponding to the power transistor in which the short-circuit has occurred, and for determining whether the short-circuit is to the positive terminal or to the negative terminal of the voltage supply.

5. A circuit according to claim 4, wherein the diagnosis-indication circuit is resettable and is arranged to indicate permanently only the first breakdown which occurs after the last reset.

2. A circuit according to claim wherein each control stage includes its own delay circuit connected to the first input and to the diagnostic circuit and arranged to delay the activation of the diagnostic circuit for a predetermined minimum period of time after the control logic signal.