Method and apparatus to enhance laser printer speed and functionality

• US 5,195,176 A
• Filed: 09/09/1991
• Issued: 03/16/1993
• Est. Priority Date: 09/09/1991
• Status: Expired due to Term

• Current Assignee: Primax Electronics Limited
• Original Assignee: Destiny Technology Corporation (Primax Electronics Limited)
• Inventors: Lung, James C. Y.
• Primary Examiner(s): Evans, Arthur G.
• Application Number:
  US07/758,984
• Time in Patent Office: 554 Days
• Field of Search: 395/101, 395/107, 395/110, 395/115, 395/112, 395/114, 395/150, 395/151, 395/164, 395/166, 395/500, 395/400, 358/404, 358/261.4, 358/444, 400/61-62, 400/171, 400/69, 340/735, 340/799
• US Class Current: 385/115
• CPC Class Codes: G06K 15/00 Arrangements for producing a permanent visual presentation of the output data , e.g. computer output printersprinting or plotting combined with another operation, e.g. with conveying, G06K17/00
• CPC Class Codes: G06K 2215/0002 Handling the output data
• CPC Class Codes: G06K 2215/0025 Removable memories, e.g. cartridges

Abstract

Method and apparatus to enhance laser printer speed and functionality including a general purpose computer, a laser printer, and a modified laser printer font cartridge, comprised of a 21-bit wide address bus, a read-only data bus, a page register, an address counter, a data counter, a font ROM module, an address-to-data converter, and a co-processor. The address bus is coupled to the laser printer and carries either address information to access locations in the co-processor or the font ROM, or data to be input to the co-processor. When the address bus carries only address information, the quantity of accessible memory locations is increased by mapping the contents of the page register with the bit code carried by the address bus. Thus, font pattern data may be read from the font ROM memory location represented by the combination of the page register contents and bit code carried by the address bus. However, if special information is loaded into the data counter, then the information carried by the address bus is actually data to be written to the co-processor. The data is transferred from the address bus, by the address-to-data converter, to the location in the co-processor represented by the combination of the contents of the page register and the address counter. The data bus is coupled to the laser printer and carries either processed font pattern data from the co-processor, or unprocessed font pattern data from the font ROM to the laser printer.

Claims

1. In a computer driven laser printer system including a general purpose computer, a laser printer, and a font cartridge, an improved font cartridge comprising:

input bus means for communicating a memory address signal or a command signal from the laser printer;

output bus means for communicating either an unprocessed font data signal or a bitmap character data signal to the laser printer;

address counter means coupled to said input bus means for receiving said memory address signal from said laser printer, and responsive to a count signal, and operative to generate an address signal for accessing a memory cell location in a processor;

address-to-data converter means coupled to said input bus means for receiving said command signal from said laser printer, and responsive to said count signal, and operative to transfer said command signal to said processor;

page register means coupled to said input bus means for receiving a page designator signal from said laser printer, and responsive to said count signal, and operative to communicate said page designator signal to said processor and to a memory device;

data counter means coupled to said input bus means for receiving a command count signal communicated from said laser printer, and operative to communicate said count signal to said address counter means, said page register means, and said address-to-data converter means;

font memory means coupled to said input bus means for receiving said memory address signal from said laser printer, and responsive to said page designator signal, and operative to transfer said unprocessed font data signal from an addressed memory location to said output bus means; and

co-processor means for processing said bitmap character data signal, responsive to said page designator signal, said address signal, and said command signal, and operative to either transfer said bitmap character data signal from a memory location within said co-processor means to said output bus means or to write said command signal to a memory location within said co-processor means, whereby the improved font cartridge, on command from said laser print controller, converts the font data stored on-board the cartridge into said bitmap character data signal.

2. An improved font cartridge as recited in claim 1 wherein said input bus means selectively communicates in a normal read cycle mode, a setup write-emulation cycle mode, or a transfer write-emulation cycle mode, as selected by the laser print controller of said laser printer.

3. An improved font cartridge as recited in claim 2 wherein said input bus means when configured for the normal read cycle mode communicates a word including a write-emulation flag bit field and an address designation field.

4. An improved font cartridge as recited in claim 3 wherein said input bus means when configured for the setup write-emulation cycle mode communicates a word including a write-emulation flag bit field, a page register means value field, a data counter means value field, and an address counter means value field.

5. An improved font cartridge as recited in claim 4 wherein said input bus means when configured for the transfer write-emulation cycle mode communicates a word including a write-emulation flag bit field and a data word field.

6. An improved font cartridge as recited in claim 1 wherein said input bus means selectively communicates in a normal read cycle mode, a first setup write-emulation cycle mode, a second setup write-emulation cycle mode, or a transfer write-emulation cycle mode, as selected by the laser print controller of said laser printer.

7. An improved font cartridge as recited in claim 6 wherein said input bus means when configured for the normal read cycle mode communicates a word including a write-emulation flag bit field and an address designation field.

8. An improved font cartridge as recited in claim 7 wherein said input bus means when configured for the first setup write-emulation cycle mode communicates a word including a write-emulation flag bit field, a page register flag bit field, a page register means value field.

9. An improved font cartridge as recited in claim 8 wherein said input bus means when configured for the second setup write-emulation cycle mode communicates a word including a write-emulation flag bit field, a page register flag bit field, a data counter means value field, and an address counter means value field.

10. An improved font cartridge as recited in claim 9 wherein said input bus means when configured for the transfer write-emulation cycle mode communicates a word including a write-emulation flag bit field and a data word field.

11. An intelligent font cartridge for connection to the font cartridge interface of a laser printer comprising:

a connector for connection to said interface;

input bus means for communicating a memory address signal or a command signal from the laser printer;

output bus means for communicating either an unprocessed font data signal or a bitmap character data signal to the laser printer;

address counter means coupled to said input bus means for receiving said memory address signal from said laser printer, and responsive to a count signal, and operative to generate an address signal for accessing a memory cell location in a processor;

address-to-data converter means coupled to said input bus means for receiving said command signal from said laser printer, and responsive to said count signal, and operative to transfer said command signal to said processor;

page register means coupled to said input bus means for receiving a page designator signal from said laser printer, and responsive to said count signal, and operative to communicate said page designator signal to said processor and to a memory device;

data counter means coupled to said input bus means for receiving a command count signal communicated from said laser printer, and operative to communicate said count signal to said address counter means, said page register means, and said address-to-data converter means;

font memory means coupled to said input bus means for receiving said memory address signal from said laser printer, and responsive to said page designator signal, and operative to transfer said unprocessed font data signal from an addressed memory location to said output bus means; and

co-processor means for processing said bitmap character data signal, responsive to said page designator signal, said address signal, and said command signal, and operative to either transfer said bitmap character data signal from a memory location within said co-processor means to said output bus means or to write said command signal to a memory location within said co-processor means, whereby the improved font cartridge, on command from said laser print controller, converts the font data stored on-board the cartridge into said bitmap character data signal.

12. An intelligent font cartridge as recited in claim 11 wherein said input bus means selectively communicates in a normal read cycle mode, a setup write-emulation cycle mode, or a transfer write-emulation cycle mode, as selected by the laser print controller of said laser printer.

13. An intelligent font cartridge as recited in claim 12 wherein said input bus means when configured for the normal read cycle mode communicates a word including a write-emulation flag bit field and an address designation field.

14. An intelligent font cartridge as recited in claim 13 wherein said input bus means when configured for the setup write-emulation cycle mode communicates a word including a write-emulation flag bit field, a page register means value field, a data counter means value field, and an address counter means value field.

15. An intelligent font cartridge as recited in claim 14 wherein said input means bus when configured for the transfer write-emulation cycle mode communicates a word including a write-emulation flag bit field and a data word field.

16. An intelligent font cartridge as recited in claim 11 wherein said input bus means selectively communicates in a normal read cycle mode, a first setup write-emulation cycle mode, a second setup write-emulation cycle mode, or a transfer write-emulation cycle mode, as selected by the laser print controller of said laser printer.

17. An intelligent font cartridge as recited in claim 16 wherein said input bus means when configured for the normal read cycle mode communicates a word including a write-emulation flag bit field and an address designation field.

18. An intelligent font cartridge as recited in claim 17 wherein said input bus means when configured for the first setup write-emulation cycle mode communicates a word including a write-emulation flag bit field, a page register flag bit field, a page register means value field.

19. An intelligent font cartridge as recited in claim 18 wherein said input bus means when configured for the second setup write-emulation cycle mode communicates a word including a write-emulation flag bit field, a page register flag bit field, a data counter means value field, and an address counter means value field.

20. An intelligent font cartridge as recited in claim 19 wherein said input bus means when configured for the transfer write-emulation cycle mode communicates a word including a write-emulation flag bit field and a data word field.

21. A method of increasing the throughput and the quantity of memory addresses accessible in a laser printer system including a general purpose computer, a laser printer, and a font cartridge, comprising the steps of:

(1) providing a font cartridge adapted to connect to a laser printer font cartridge interface and including an input bus, an output bus, an address counter, an address-to-data converter, a page register, a data counter, a font memory having a predetermined quantity of accessible memory addresses, and a co-processor;

(2) generating a communication word having a first portion of bits, at least one data bit of which constitutes a signal flag the state of which determines whether said communication word corresponds to a write-emulation cycle instruction or a read cycle instruction, and having a second portion including a plurality of data bits which

(a) comprise page register information, data counter information, and address counter information when said signal flag is the first occurrence, in a sequence, of a first data state, and

(b) comprise transferred data information when said signal flag is of said first data state and the current communication word immediately follows a communication word the signal flag of which is of said first data state, and

(c) comprise address information when said signal flag is of a second data state;

(3) inputting a first write-emulation cycle communication word to said input bus to load said page register information into said page register, said data counter information into said data counter, said address counter information into said address counter, thereby setting up said address counter, said data counter, and said page register for the next cycle;

(4) inputting a subsequent write-emulation cycle communication word, or a second write-emulation cycle communication word, or a read cycle communication word to said input bus;

(5) determining if the communication word input to said input bus is a first write-emulation cycle communication word, or a second write-emulation cycle communication word, or a read cycle communication word;

(6) performing a reset operation, a read operation, or a write operation depending upon the type of communication word input in the preceding step.

22. A method as recited in claim 21 wherein said step of providing said font memory having a predetermined quantity of accessible memory addresses includes creating a page set having a plurality of page designators, segmenting the total address space of said modified font cartridge into a plurality of address segments, and assigning to an individual address segment each of the plurality of said page designators.

23. A method as recited in claim 21 wherein said step of determining if the communication word input to said input bus is a first write-emulation cycle communication word, or a second write-emulation cycle communication word, or a read cycle communication word, includes:

(a) reading the contents of said data counter;

(b) if said data counter contents are at a third data state then causing the data bits in said second portion to be input through said address-to-data converter to said co-processor causing it to output to said output bus the corresponding bitmap character data;

(c) if said data counter contents are at a fourth data state then causing said signal flag to be read;

(d) reading the state of said signal flag;

(e) if the state of said signal flag is at said first data state then causing said page register information to be loaded into said page register, said data counter information to be loaded into said data counter, and said address counter information to be loaded into said address counter, thereby setting up said address counter, said data counter, and said page register for the next cycle;

(f) if the state of said signal flag is at said second data state then causing the data bits in said second portion to address a particular memory location in said font memory causing it to output the contents thereof to said output bus.

24. A method of increasing the throughput and the quantity of memory addresses accessible in a laser printer system including a general purpose computer, a laser printer, and a font cartridge, comprising the steps of:

(1) providing a font cartridge adapted to connect to a laser printer font cartridge interface and including an input bus, an output bus, an address counter, an address-to-data converter, a page register, a data counter, a font memory having a predetermined quantity of accessible memory addresses, and a co-processor;

(2) generating a communication word having a first portion of bits, at least one data bit of which constitutes a first signal flag the state of which determines whether said communication word corresponds to a write-emulation cycle instruction or a read cycle instruction, and having a second portion of bits, at least one data bit of which constitutes a second signal flag the state of which determines whether said communication word corresponds to a first write-emulation cycle instruction or a second write-emulation cycle instruction, and having a third portion including a plurality of data bits which

(a) comprise page register information when said first and second signal flags are both set to a first data state and it is the first occurrence, in a sequence, of said first data state, and

(b) comprise data counter information and address counter information when said first signal flag is set to said first data state while said second signal flag is set to a second data state and it is the second occurrence of said first data state and the first occurrence of said second data state, and

(c) comprise transferred data information when said first signal flag is of said first data state and the current communication word immediately follows a communication word the first signal flag of which is of said first data state, and

(d) comprise address information when said first signal flag is of said second data state;

(3) inputting a first write-emulation cycle communication word to said input bus to load said page register information into said page register, thereby setting up said page register for the next cycle;

(4) inputting a second write-emulation cycle communication word to said input bus to load said data counter information into said data counter and said address counter information into said address counter, thereby setting up said address counter and said data counter for the next cycle;

(5) inputting a subsequent first write-emulation cycle communication word, or a subsequent second write-emulation cycle communication word, or a third write-emulation cycle communication word, or a read cycle communication word to said input bus;

(6) determining if the communication word input to said input bus is a first write-emulation cycle communication word, or a second write-emulation cycle communication word, or a third write-emulation cycle communication word, or a read cycle communication word;

(7) performing a first reset operation, a second reset operation, a read operation, or a write operation depending upon the type of communication word input in the preceding step.

25. A method as recited in claim 24 wherein said step of providing said font memory having a predetermined quantity of accessible memory addresses includes creating a page set having a plurality of page designators, segmenting the total address space of said modified font cartridge into a plurality of address segments, and assigning to an individual address segment each of the plurality of said page designators.

26. A method as recited in claim 24 wherein said step of determining if the communication word input to said input bus is a first write-emulation cycle communication word, or a second write-emulation cycle communication word, or a third write-emulation cycle communication word, or a read cycle communication word, includes:

(a) reading the contents of said data counter;

(b) if said data counter contents are at a third data state then causing the data bits in said third portion to be input through said address-to-data converter to said co-processor causing it to output to said output bus the corresponding bitmap character data;

(c) if said data counter contents are at a fourth data state then causing said first signal flag to be read;

(d) reading the state of said first signal flag;

(e) if the state of said first signal flag is at said second data state then causing the data bits in said third portion to address a particular memory location in said font memory causing it to output the contents thereof to said output bus;

(f) if the state of said first signal flag is at said first data state then causing the contents of said second signal flag to be read;

(g) reading the state of said second signal flag;

(h) if the state of said second signal flag is at said first data state then causing said page register information to be loaded into said page register, thereby setting up said page register for next cycle;

(i) if the state of said second signal flag is at said second data state then causing said data counter information to be loaded into said data counter, and said address counter information to be loaded into said address counter, thereby setting up said address counter, and said page register for the next cycle.

27. A method of increasing the quantity of memory addresses accessible in a font cartridge and for emulating a write cycle to said font cartridge, comprising the steps of:

(1) providing an intelligent font cartridge adapted to connect to a laser printer font cartridge interface and including an input bus, an output bus, an address counter, an address-to-data converter, a page register, a data counter, a font memory having a predetermined quantity of accessible memory addresses, and a co-processor;

(2) generating a communication word having a first portion of bits, at least one data bit of which constitutes a signal flag the state of which determines whether said communication word corresponds to a write-emulation cycle instruction or a read cycle instruction, and having a second portion including a plurality of data bits which

(a) comprise page register information, data counter information, and address counter information when said signal flag is the first occurrence, in a sequence, of a first data state, and

(b) comprise transferred data information when said signal flag is of said first data state and the current communication word immediately follows a communication word the signal flag of which is of said first data state;

(3) inputting a first write-emulation cycle communication word to said input bus to load said page register information into said page register, said data counter information into said data counter, said address counter information into said address counter, thereby setting up said address counter, said data counter, and said page register for the next cycle;

(4) inputting a subsequent write-emulation cycle communication word, or a second write-emulation cycle communication word to said input bus;

(5) determining if the communication word input to said input bus is a first write-emulation cycle communication word, or a second write-emulation cycle communication word;

(6) performing a reset operation, or a write operation depending upon the type of communication word input in the preceding step.

28. A method as recited in claim 27 wherein said step of providing said font memory having a predetermined quantity of accessible memory addresses includes creating a page set having a plurality of page designators, segmenting the total address space of said modified font cartridge into a plurality of address segments, and assigning to an individual address segment each of the plurality of said page designators.

29. A method as recited in claim 27 wherein said step of determining if the communication word input to said input bus is a first write-emulation cycle communication word, or a second write-emulation cycle communication word, includes:

(a) reading the contents of said data counter;

(b) if said data counter contents are at a third data state then causing the data bits in said second portion to be input through said address-to-data converter to said co-processor causing it to output to said output bus the corresponding bitmap character data;

(c) if said data counter contents are at a fourth data state then causing said signal flag to be read;

(d) reading the state of said signal flag;

(e) if the state of said signal flag is at said first data state then causing said page register information to be loaded into said page register, said data counter information to be loaded into said data counter, and said address counter information to be loaded into said address counter, thereby setting up said address counter, said data counter, and said page register for the next cycle.

30. A method of increasing the quantity of memory addresses accessible in a font cartridge and for emulating a write cycle to said font cartridge, comprising the steps of:

(1) providing an intelligent font cartridge adapted to connect to a laser printer font cartridge interface and including an input bus, an output bus, an address counter, an address-to-data converter, a page register, a data counter, a font memory having a predetermined quantity of accessible memory addresses, and a co-processor;

(2) generating a communication word having a first portion of bits, at least one data bit of which constitutes a first signal flag the state of which determines whether said communication word corresponds to a write-emulation cycle instruction or a read cycle instruction, and having a second portion of bits, at least one data bit of which constitutes a second signal flag the state of which determines whether said communication word corresponds to a first write-emulation cycle instruction or a second write-emulation cycle instruction, and having a third portion including a plurality of data bits which

(a) comprise page register information when said first and second signal flags are both set to a first data state and it is the first occurrence, in a sequence, of said first data state, and

(b) comprise data counter information and address counter information when said first signal flag is set to said first data state while said second signal flag is set to a second data state and it is the second occurrence of said first data state and the first occurrence of said second data state, and

(c) comprise transferred data information when said first signal flag is of said first data state and the current communication word immediately follows a communication word the first signal flag of which is of said first data state;

(3) inputting a first write-emulation cycle communication word to said input bus to load said page register information into said page register, thereby setting up said page register for the next cycle;

(4) inputting a second write-emulation cycle communication word to said input bus to load said data counter information into said data counter and said address counter information into said address counter, thereby setting up said address counter and said data counter for the next cycle;

(5) inputting a subsequent first write-emulation cycle communication word, or a subsequent second write-emulation cycle communication word, or a third write-emulation cycle communication word;

(6) determining if the communication word input to said input bus is a first write-emulation cycle communication word, or a second write-emulation cycle communication word, or a third write-emulation cycle communication word;

(7) performing a first reset operation, a second reset operation, or a write operation depending upon the type of communication word input in the preceding step.

31. A method as recited in claim 30 wherein said step of providing said font memory having a predetermined quantity of accessible memory addresses includes creating a page set having a plurality of page designators, segmenting the total address space of said modified font cartridge into a plurality of address segments, and assigning to an individual address segment each of the plurality of said page designators.

32. A method as recited in claim 30 wherein said step of determining if the communication word input to said input bus is a first write-emulation cycle communication word, or a second write-emulation cycle communication word, or a third write-emulation cycle communication word, includes:

(a) reading the contents of said data counter;

(b) if said data counter contents are at a third data state then causing the data bits in said third portion to be input through said address-to-data converter to said co-processor causing it to output to said output bus the corresponding bitmap character data;

(c) if said data counter contents are at a fourth data state then causing said first signal flag to be read;

(d) reading the state of said first signal flag;

(e) if the state of said first signal flag is at said first data state then causing the contents of said second signal flag to be read;

(f) reading the state of said second signal flag;

(g) if the state of said second signal flag is at said first data state then causing said page register information to be loaded into said page register, thereby setting up said page register for next cycle;

(h) if the state of said second signal flag is at said second data state then causing said data counter information to be loaded into said data counter, and said address counter information to be loaded into said address counter, thereby setting up said address counter, and said page register for the next cycle.