Method for fabricating semiconductor circuits

• US 5,196,233 A
• Filed: 01/18/1989
• Issued: 03/23/1993
• Est. Priority Date: 01/18/1989
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Inventors: Bishop, William A., Chan, Tsiu C.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Nguyen, Tuan
• Application Number:
  US07/298,530
• Time in Patent Office: 1,525 Days
• Field of Search: 437/46, 437/47, 437/186, 437/162, 437/48, 437/49, 437/52, 437/56, 437/60, 437/918
• US Class Current: 438/384
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/15 comprising a resistor load element

Abstract

A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.

Claims

1. A method for making a resistive load element for a semiconductor integrated circuit device, comprising the steps of:

forming a first layer of polycrystalline silicon signal lines over the integrated circuit;

forming an insulating layer over the integrated circuit;

forming contact openings in the insulating layer, wherein a selected set of such openings expose portions of the first layer of signal lines and an underlying substrate in each opening;

forming a second layer of polycrystalline silicon having a first conductivity type over the surface of the integrated circuit;

within the second polycrystalline layer, forming regions having a second conductivity type;

patterning the second polycrystalline layer to form elongate elements having a region of the first conductivity type between two separate regions of the second conductivity type, wherein current flowing through the element passes successively through second conductivity type, then first conductivity type, then second conductivity type regions, and further wherein the elongate elements make electrical contact with both the underlying substrate and with the exposed first polycrystalline silicon layer portions in the contact openings, thereby forming a shared contact.

2. The method of claim 1, wherein said second conductivity type region forming step comprises the steps of:

patterning a layer of photoresist over the second polycrystalline silicon layer; and

doping exposed regions of the second polycrystalline silicon layer with impurities, which convert the polycrystalline silicon to the second conductivity type, using ion implantation.

3. The method of claim 2, wherein the first conductivity type is N-type and the second conductivity type is P-type.

4. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type. f