Method of fabricating silicon-based carriers

• US 5,196,377 A
• Filed: 08/20/1991
• Issued: 03/23/1993
• Est. Priority Date: 12/20/1990
• Status: Expired due to Term

• Current Assignee: Silicon Graphics International Corporation (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Eberlein, Delvin D., Wagner, John J., Chojnacki, Thomas P.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US07/747,523
• Time in Patent Office: 581 Days
• Field of Search: 437/225, 437/209, 437/211, 437/215, 437/228, 437/974, 357/71, 357/55, 148/DIG. 135
• US Class Current: 438/384
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Silicon is used to create multi-chip carriers for integrated circuits. The process of fabricating the carriers uses standard integrated circuit fabrication equipment. Cavities are etched into a silicon wafer, metallization or polysilicon is deposited to electrically interconnect the cavities, and integrated circuit die are placed in the cavities. Traces connecting the integrated circuits are buried in channels formed in the silicon, which can be doped and biased to provide enhanced isolation between traces as well as control over the electrical characteristics of the traces. The traces can be formed in multiple layers of material placed on the wafer to provide additional communication capacity in the carriers.

Claims

1. A method of fabricating at least one integrated circuit chip carrier, each chip carrier having at least one cavity for holding an integrated circuit chip, comprising the steps of:

(a) providing a keyed wafer from silicon;

(b) forming at least one channel in a top surface of the wafer, each channel being elongate and extending from proximate the at least one cavity to proximate a periphery of the chip carrier;

(c) depositing a first conductive material in the at least one channel to form traces;

(d) fabricating a plurality of bonding pads from a second conductive material on the top surface of the wafer, each bonding pad being in electrical communication with at least one of the traces;

(e) depositing a passivation layer on the top surface of the wafer, the traces and the plurality of bonding pads;

(f) etching the at least one cavity in the top surface of the wafer, each cavity being sized to contain at least one integrated circuit chip; and

(g) partially etching the passivation layer so that at least one of the plurality of bonding pads is uncovered for bonding.

2. The method of claim 1, wherein each of the first and second conductive materials comprises a first and second metal.

3. The method of claim 2, wherein the first and second metals are the same and are selected from the group consisting of gold or aluminum.

4. The method of claim 1, wherein the first conductive material comprises doped polysilicon.

5. The method of claim 1, further comprising the step of electrically isolating the at least one channel from the keyed wafer by oxidizing the surfaces of the at least one channel.

6. The method of claim 1, further comprising the steps of:

a) doping the keyed wafer to make it electrically conductive; and

b) electrically isolating the traces from the keyed wafer before depositing the first conductive material in the at least one channel.

7. The method of claim 1, further comprising the steps of:

a) depositing a layer of doped polysilicon on the top surface of the keyed base wafer before the step of forming the at least one channel, the doped polysilicon providing electrically conductive material between the traces; and

b) electrically isolating the traces from the doped polysilicon before depositing the first conductive material in the at least one channel.

8. The method of claim 1, further comprising the step depositing at least one barrier material on the first conductive material, the barrier material providing a diffusion barrier between the first conductive material and the second conductive material.

9. The method of claim 8, wherein the step of depositing a first conductive material further comprises depositing gold and the step of fabricating a plurality of bonding pads further comprises fabricating the plurality of bonding pads from aluminum.

10. The method of claim 8, wherein the step of depositing a barrier material further comprises selecting a barrier material from the group consisting of titanium-tungsten and titanium nitride.

23. The method of claim 2 , wherein the step of electrically isolating the shielding layer further comprises:

(1) providing a first layer of a non-conductive material on the raised top surface of the preceding trace layer before depositing the shielding layer; and

(2) providing a second layer of a non-conductive material on a top surface of the shielding layer before depositing the succeeding trace layer.

11. A method of fabricating an integrated circuit chip carrier, the chip carrier having a cavity for holding an integrated circuit chip, comprising the steps of:

(a) providing a keyed base wafer from silicon;

(b) forming a channel in a top surface of the keyed base wafer, the channel being elongate and extending from proximate the cavity to proximate a periphery of the chip carrier;

(c) electrically isolating the channel from the keyed base wafer through oxidation of the surfaces of the channel;

(d) depositing a first conductive material in the channel to form a trace;

(e) fabricating a bonding pad on the top surface of the keyed base wafer, the bonding pad being fabricated from a second conductive material and further being in electrical communication with the trace;

(f) depositing at least one barrier material on the first conductive material to provide a diffusion barrier between the first conductive material of the trace and the second conductive material of the bonding pad;

(g) depositing a layer of passivation material on (1) the top surface of the keyed base wafer, (2) the trace, and (3) the bonding pad;

(h) etching the cavity in the top surface of the wafer, the cavity being sized to contain at least one integrated circuit chip; and

(i) removing the passivation material so that at least a portion of the bonding pad is uncovered for bonding to other devices proximate the chip carrier via known bonding methods.

12. A method of fabricating n integrated circuit chip carrier, the chip carrier having a cavity for holding an integrated circuit chip, comprising the steps of:

(a) providing a keyed base wafer having a top surface;

(b) forming a plurality of trace layers on the top surface of the keyed base wafer, a first trace layer being formed in the top surface of the keyed base wafer, with traces in the first trace layer being formed in elongate channels formed in the top surface of the keyed base wafer, after formation of the first trace layer succeeding trace layers are formed above preceding trace layers and an uppermost trace layer is formed last having an uppermost raised top surface, the formation of each of the plurality of trace layers above the first trace layer further comprising the substeps of;

(1) depositing layer material on the top surface of the keyed base wafer to form a raised top surface;

(2) forming a channel in the raised top surface, the channel being elongate and extending from proximate the cavity to proximate a periphery of the chip carrier; and

(3) depositing conductive trace material in the channel to form a trace;

(c) fabricating a bonding pad on the uppermost raised top surface, the bonding pad being in electrical communication with the trace of the uppermost trace layer;

(d) depositing a layer of passivation material on (1) the uppermost raised top surface, (2) the trace of the uppermost raised top surface, and (3) the bonding bad;

(e) providing a cavity in a selected area of the integrated circuit chip carrier, the cavity being sized to contain at least one integrated circuit chip; and

(f) removing a portion of the passivation material so that at least a portion of the bonding pad is uncovered for bonding to other devices proximate the chip carrier via known bonding methods.

13. The method of claim 12, wherein the step of providing a cavity further comprises removing the plurality of trace layers from the selected area of the top surface of the keyed base wafer.

14. The method of claim 12, wherein the step of depositing the layer material of at least one of the plurality of trace layers further comprises depositing polysilicon as the layer material.

15. The method of claim 12, wherein the step of depositing the layer material of at least one of the plurality of trace layers further comprises depositing electrically conductive material as the layer material.

16. The method of claim 15, wherein the step of depositing the layer material of at least one of the plurality of trace layers further comprises depositing doped polysilicon as the layer material.

17. The method of claim 15, further comprising the step of electrically isolating the conductive trace material from the electrically conductive material deposited as the layer material.

18. The method of claim 17, wherein the step of electrically isolating further comprises oxidizing the surfaces of the channel formed in the at least one of the plurality of trace layers, the oxidizing occurring before depositing the conductive trace material in the channel formed in the at least one of the plurality of trace layers.

19. The method of claim 12, further comprising the steps of:

(1) forming a channel in the top surface of the keyed base wafer forming the first trace layer; and

(2) depositing at least two conductive material in the channel formed in the top surface of the keyed base wafer to form a trace in the channel formed in the top surface of the keyed base wafer.

20. The method of claim 19, wherein the step of depositing at least one conductive material further comprises depositing doped polysilicon.

21. The method of claim 12, further comprising the step of depositing a shielding layer between a succeeding trace layer and a preceding trace layer to provide electrical shielding therebetween.

22. The method of claim 21, further comprising the step of electrically isolating the shielding layer from the succeeding trace layer and preceding trace layer.

24. The method of claim 12, wherein the step of forming a plurality of trace layers further comprises forming a via between at least one succeeding trace layer and at least one preceding trace layer such that the trace in the at least one succeeding trace layer is in electrical communication with the trace in the at least one preceding trace layer.

25. The method of claim 12, wherein the step of forming a plurality of trace layers further comprises forming a passive electrical component in at least one of the plurality of trace layers, the component being in electrical communication with a trace.

26. The method of claim 25, further comprising the step of selecting the passive component from the group consisting of resistors and capacitors.

27. The method of claim 12, wherein the step of depositing conductive trace material further comprises depositing a trace metal in the channel formed in the uppermost trace layer.

28. The method of claim 27, wherein the step of forming a plurality of trace layers further comprises depositing doped polysilicon as the conductive trace material in the plurality of trace layers formed below the uppermost trace layer.

29. The method of claim 27, further comprising the step of selecting the trace metal from the group consisting of gold and aluminum.

30. The method of claim 27, further comprising the step of depositing at least one barrier material on the trace metal, the barrier material providing a diffusion barrier between the trace metal and the bonding pad.

31. The method of claim 30, wherein the step of depositing conductive trace material in the uppermost raised top surface further comprises depositing gold, and further wherein the step of fabricating the bonding pad further comprises fabricating the bonding pad from aluminum.

32. The method of claim 31, wherein the step of depositing at least one barrier material further comprises selecting a barrier material from the group consisting of titanium tungsten and titanium nitride.

33. A method of fabricating an integrated circuit chip carrier, the chip carrier having a cavity for holding an integrated circuit chip, comprising the steps of:

(a) providing a keyed base wafer having a top surface;

(b) forming a plurality of trace layers on the top surface of the keyed base wafer, a first trace layer being formed in the top surface of the keyed base wafer, with traces in the first trace layer being formed in elongate channels formed in the top surface of the keyed base wafer, after formation of the first trace layer succeeding trace layers are formed above preceding trace layers and an uppermost trace layer is formed last having an uppermost raised top surface, the formation of each of the plurality of trace layers above the first trace layer further comprising the substeps of;

(1) depositing polysilicon to form a raised top surface;

(2) forming a channel in the raised top surface, the channel being elongate and extending from proximate the cavity to proximate a periphery of the chip carrier;

(3) depositing conductive trace material in the channel to form a trace; and

(4) electrically isolating the trace from the polysilicon;

(c) fabricating a bonding pad on the uppermost raised top surface, the bonding pad being in electrical communication with the trace of the uppermost trace layer;

(d) depositing a layer of passivation material on (1) the uppermost raised top surface, (2) the trace of the uppermost raised top surface, and (3) the bonding pad;

(e) providing a cavity in a selected area of the integrated circuit chip carrier, the cavity being sized to contain at least one integrated circuit chip; and

(f) removing a portion of the passivation material so that at least a portion of the bonding pad is uncovered for bonding to other devices proximate the chip carrier via known bonding methods.