Shadow ram cell having a shallow trench eeprom

• US 5,196,722 A
• Filed: 03/12/1992
• Issued: 03/23/1993
• Est. Priority Date: 03/12/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Lam, Chung H., Cronin, John E., Bergendahl, Albert S., Kalter, Howard L., Kenney, Donald M., Lee, Hsing-San
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US07/848,913
• Time in Patent Office: 376 Days
• Field of Search: 357/23.5, 357/23.6, 357/55
• US Class Current: 257/304
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

Claims

1. A semiconductor device memory array formed on a semiconductor substrate, comprising:

a multiplicity of DRAM cells, each of said DRAM cells having a FET with a gate electrode and first and second diffusion regions, and a storage capacitor having first and second storage electrodes, said storage electrode being coupled to said first diffusion region of said FET;

and a multiplicity of EEPROM cells, each having a floating gate disposed in a trench in said semiconductor substrate running between respective ones of said multiplicity of DRAM cells, each of said multiplicity of EEPROM cells having a first controlled electrode connected to said first diffusion region of a respective one of said FETs of a respective one of said DRAM cells, so that a logic state stored by said storage capacitor modulates a charge region in a portion of said substrate adjacent to said floating gate to control a charge stored in said floating gate.

2. A memory array according to claim 1 wherein said storage capacitor comprises a stacked capacitor.

3. A memory array according to claim 1 wherein said storage capacitor comprises a deep trench storage capacitor.

4. A semiconductor device memory array according to claim 3 wherein said multiplicity of FETs are disposed in rows and columns, and wherein said trenches run diagonally between respective ones of said multiplicity of DRAM devices.

5. A memory array according to claim 4 wherein said multiplicity of DRAM cells are in a quarter-pitched array.

6. An array according to claim 5 wherein said multiplicity of EEPROM cells comprise a pair of continuous polysilicon structures disposed within said shallow trench that function as program and recall gates and a plurality of discontinuous polysilicon structures disposed within said shallow trench that function as floating gates.

7. An array according to claim 6 wherein said polysilicon floating gates are disposed along opposite walls of said shallow trench and separated from a portion of the silicon substrate adjacent to said trench by a dielectric material such that when a negative charge resides on one of said floating gates, a vertically oriented inversion is more difficult to induce in said substrate adjacent said floating gate.

8. An array according to claim 7 wherein said continuous polysilicon program and recall gate structures are parallel and separated by a dielectric material, said recall gate being disposed along the bottom of said shallow EEPROM trench and extending below a P/N boundary in said silicon substrate.

9. An array according to claim 8 wherein said floating gate structures are separated from said program and recall gate structures by a material that permits Fowler-Nordheim tunneling.

10. An array according to claim 9 wherein said material that permits Fowler-Nordheim tunneling comprises silicon rich nitride.

11. A semiconductor device memory array according to claim 9 wherein said material that permits Fowler-Nordheim tunneling comprises silicon rich oxide.

12. A semiconductor device memory array according to claim 1 wherein a single external power supply voltage operates both said DRAM cells and said EEPROM cells.

13. A memory cell array formed relative to a surface of a semiconductor substrate, said memory cell array comprising:

(a) at least four rectangular trenches aligned in two parallel rows offset such that corresponding elements of said rectangular trenches fall on a diagonal line which is at about 45°

to said parallel rows, each rectangular trench containing an electrode surrounded by an insulator;

(b) at least one elongated, linear trench oriented parallel to said diagonal line, said elongated trench having first and second side portions and a bottom portion;

(c) at least one first electrode disposed in one of said elongated trenches such that each trench contains a first electrode, each of said first electrodes being coupled to a voltage source and each of said first electrodes having a first surface portion;

(d) a plurality of second electrodes, disposed at said first side portion of one of said elongated trenches such that each second electrode is adjacent one rectangular trench on its side of said elongated trench, each of said second electrodes having a second surface portion disposed adjacent said first surface portion of a respective one of said first electrodes for receiving injected electrons therefrom, and each of said second electrodes having a third surface portion;

(e) a plurality of third electrodes disposed at said second side portion of one of said elongated trenches such that each third electrode is adjacent one rectangular trench on its side of said elongated trench, each of said third electrodes having a second surface portion disposed adjacent said first surface portion of a respective one of said first electrodes for receiving injected electrons therefrom, and each of said third electrodes having a third surface portion;

(f) a fourth electrode disposed at said upper portion of one of said elongated trenches, having a fourth surface portion disposed adjacent said third surface portions of respective ones of said second and third electrodes for receiving electrons injected therefrom; and

(g) a diffusion region, said diffusion region being adjacent to said elongated trench and disposed between adjacent ones of said rectangular trenches, said diffusion region being coupled to a signal source.

14. A memory cell array according to claim 13 further comprising a plurality of elongated, linear diagonal, substantially parallel trench segments formed in said surface of said substrate, each of said elongated trench segments connected by connecting trench segments parallel to said rows of rectangular trenches so as to form a single, continuous trench passing adjacent a plurality of said rectangular trenches in said array.

15. A memory cell array according to claim 13 wherein electrical connection between said first electrode and said first electrode voltage source and said fourth electrode and said fourth electrode voltage source is provided in said connecting trench segments.

16. A memory cell array according to claim 15 further characterized in that:

(a) said semiconductor substrate is a bilayered substrate;

(b) said elongated trench cuts through one corner of each of said rectangular trenches, and said elongated trench bottom is below a boundary between layers of said bilayered semiconductor substrate;

(c) said first electrode is disposed at said bottom portion of one of said elongated trenches;

(d) said fourth electrode is disposed at said upper portion of one of said elongated trenches and each of said fourth electrodes has a fourth surface portion disposed adjacent said third surface portions of respective ones of said second and third electrodes for receiving electrons injected therefrom; and

(e) said diffusion region is additionally coupled to said electrodes in said rectangular trenches.

17. A memory cell array according to claim 16 wherein said memory cell comprises a DRAM cell and an EEPROM cell;

said first electrodes comprise recall gates, said second electrodes and said third electrodes comprise floating gates, said fourth electrodes comprise program gates, and said rectangular trench electrodes comprise DRAM capacitors.

18. An EEPROM memory array formed in a semiconductor substrate, said EEPROM array comprising:

(a) a groove formed in said substrate;

(b) a first continuous electrode coupled to a first voltage source;

(c) a second continuous electrode coupled to a second voltage source;

(d) a plurality of discontinuous electrodes;

(e) an electrically insulating material separating all of said electrodes from said substrate, said first and second electrodes from each other, and said discontinuous electrodes from one another; and

(f) a material that allows electrons to tunnel between said discontinuous electrodes and said first and second electrodes.

19. An EEPROM according to claim 18 wherein said first electrode is disposed at a bottom of said groove, said second electrode is disposed at a top of said groove and said discontinuous electrodes are disposed along two sides of said groove.

20. An EEPROM according to claim 19 wherein said first electrode functions as a recall gate, second electrode functions as a program gate, and said discontinuous electrodes function as floating

21. An EEPROM according to claim 19 wherein said groove passes through an array of individual memory cells on said substrate and electrical connections are made to said first and second continuous electrodes in a region outside said array of individual memory cells.

22. An EEPROM cell comprising a first electrode which functions as a recall gate, a second electrode which functions as a program gate, and at least two third electrodes which function as floating gates wherein said first and second electrodes are T-shaped in cross section, said first electrode is in inverted T orientation, said second electrode is in upright T orientation, the main axes of both electrodes are aligned vertically and said two third electrodes occupy regions on opposite sides of said vertically aligned first and second electrodes within a vertical region defined by horizontal elements of said T- shaped first and second electrodes.

23. A coupled DRAM-EEPROM circuit comprising:

(a) an input terminal;

(b) a control terminal;

(c) a field effect transistor (FET) having a current channel and a control electrode for receiving a signal;

a first end of said channel being connected to said input terminal;

(d) a storage capacitor having an input coupled to a second end of said channel;

(e) a second FET having a control electrode for receiving a signal, a floating gate, and a current channel, a first end of said second FET current channel being coupled to said second end of said first FET channel and to said capacitor;

(f) a third FET having a control electrode for receiving a signal and a current channel, a first end of said third FET channel being coupled to a second end of said second FET channel;

second end of said third FET channel being coupled to a signal node a second end of said third FET channel being coupled to said control terminal;

(g) said floating gate of said second FET being capable of receiving electrons by tunneling from said third FET control electrode;

said floating gate of said second FET being capable of discharging electrons by tunneling to said second FET control electrode; and

(h) said storage capacitor having a higher capacitance than a capacitive load provided by said second and third FETs.

24. A coupled DRAM-EEPROM circuit according to claim 23 whereby when said first FET control electrode and said third FET control electrode are at ground, said storage capacitor and said second FET are isolated, allowing said second FET control electrode to modulate a transfer of electrons to said floating gate from said third FET electrode and from said floating gate to said second FET electrode as a function of a condition of said storage capacitor.

25. A coupled DRAM-EEPROM circuit according to claim 23 wherein said first FET and said storage capacitor comprise a DRAM, said second and third FETs comprise an EEPROM which can exist in one of two states and said storage capacitor controls the state of said EEPROM.

26. A coupled DRAM-EEPROM circuit according to claim 25 wherein said second FET control electrode and said third FET control electrodes are controlled independently at ground or at a single control signal voltage.

27. A coupled DRAM-EEPROM circuit according to claim 26 wherein said single control voltage is between ten and eighteen volts.

28. A coupled DRAM-EEPROM circuit according to claim 27 wherein said control voltage is supplied by an on-chip voltage device.

29. A shadow DRAM cell, comprising:

a first FET having a gate electrode coupled to a word line and first and second controlled electrodes said first controlled electrode being coupled to a bit line;

a storage capacitor having first and second electrodes, one of said electrodes of said storage capacitor being coupled to said second controlled electrode of said first FET; and

a second FET having a floating gate, a first control gate disposed on said floating gate, and first and second controlled electrodes, said first controlled electrode of said second FET being coupled to said second controlled electrode of said first FET.

30. The shadow DRAM cell according to claim 29 wherein said second FET further comprises a second control gate disposed on said floating gate.

31. The shadow DRAM cell according to claim 29 wherein said first and second control gates receive first and second control signals, respectively, to respectively inject charge into or remove charge from said floating gate as a function of a logic state stored by aid storage capacitor.

32. An EEPROM cell formed in a semiconductor substrate having a trench formed therein having a lower portion, an upper portion, and first and second sides, comprising:

a first electrode formed within the bottom portion of the trench;

a second electrode formed within the trench and abutting at least the first side of the trench and a portion of said first electrode for receiving electrons injected therefrom;

a third electrode formed at least partially within the trench, and abutting said second electrode for receiving tunneling electrons injected therefrom, and

a diffusion region extending from the surface of the substrate and abutting at least the side of the trench.

33. The EEPROM cell according to claim 32 wherein said diffusion region comprises a controlled electrode of an FET formed on a portion of said substrate abutting said trench.

34. The EEPROM cell according to claim 33 wherein said diffusion region is coupled to a storage electrode of a capacitor.

35. The EEPROM cell according to claim 32 wherein a plurality of said EEPROM cells are formed within an elongated trench, wherein said first and third electrodes comprise elongated conductors that run along the entire length of said trench, and wherein said second electrode comprises a discontinuous conductor having a plurality of respective portions separated by an insulator.