System and method for setting capacitive constraints on synthesized logic circuits

• US 5,197,015 A
• Filed: 12/20/1990
• Issued: 03/23/1993
• Est. Priority Date: 12/20/1990
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Hartoog, Mark R., Schaefer, Thomas J., Shur, Robert D.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/631,600
• Time in Patent Office: 824 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/104
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

In a computer aided design system, capacitative constraints are defined for the nodes of an integrated circuit. A netlist specifies the integrated circuit'"'"'s components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit'"'"'s components. The process begins by assigning a time delay value and a corresponding initial maximum capacitance value to each circuit node, consistent with the specified timing constraints. Next, a routing difficulty value for the entire circuit, equal to a sum of routing difficulty values associated with the circuits'"'"'s nodes is computed. Each routing difficulty value is a predefined function of the maximum capacitance value for a corresponding node and the number of circuit components coupled to that node. Then, the following steps are repeated until changes in the computed routing difficulty value for the entire circuit meet predefined criteria. Beginning with components coupled to output nodes and progressing toward components adjacent input nodes, the time delay associated with a component'"'"'s output node is decreased by decreasing its maximum capacitance value and the time delay associated with each of component'"'"'s input node is increased by a corresponding amount. Then the routing difficulty value is recomputed and the changed time delays are retained only when the change has caused the computed routing difficulty to decrease.

Claims

1. A method of synthesizing an integrated circuit, the steps of the method comprising:

receiving and storing in a computer memory a netlist denoting a list of components in an integrated circuit and a set of nodes interconnecting said components;

each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit;

assigning a time delay value and a corresponding maximum capacitance value to each said node;

computing a routing difficulty value, comprising a sum of routing difficulty values associated with each of said nodes in said integrated circuit;

repeating the following steps until changes in said computed routing difficulty value meet predefined criteria;

selecting one of said components;

decreasing said time delay and maximum capacitance value associated with a node coupled to an output port of said component and increasing by corresponding amounts said time delay and maximum capacitance value associated with nodes coupled to input ports of said component;

recomputing said routing difficulty value; and

retaining said changed time delay and maximum capacitance values only if said recomputed routing difficulty value is smaller than its previous value; and

passing said netlist and maximum capacitance values to a silicon compiler and automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values;

whereby said maximum capacitance values for said integrated circuit are automatically adjusted so as to reduce the difficulty of routing connections between said integrated circuit'"'"'s components.

2. The method set forth in claim 1, each said node having a fanout value corresponding to the number of said component inputs ports coupled to said node;

wherein said computed routing difficulty value is a predefined function of said maximum capacitance value for a corresponding node and said fanout value of said node.

3. The method set forth in claim 1, wherein said selecting step first selects components coupled to said output nodes of said integrated circuit and progresses toward components adjacent said input nodes.

4. A computer aided design system for synthesizing an integrated circuit, comprising:

input means and storage means for receiving and storing in a computer memory a netlist denoting a list of components in an integrated circuit and a set of nodes interconnecting said components;

each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit;

initial value assignment means, coupled to said storage means, for assigning a time delay value and a corresponding maximum capacitance value to each said node;

layout difficulty function means for computing a routing difficulty value, comprising a sum of routing difficulty values associated with each of said nodes in said integrated circuit;

optimization means, coupled to said initial value assignment means, said storage means, and said layout difficulty function means, for repeatedly

selecting one of said components,

decreasing said time delay and maximum capacitance value associated with a node coupled to an output port of said component and increasing by corresponding amounts said time delay and maximum capacitance value associated with each node coupled to an input port of said component, calling

calling said layout difficulty function means to recompute said routing difficulty value; and

retaining said changed time delay and maximum capacitance values only if said recomputed routing difficulty value is smaller than its previous value; and

means for passing said netlist and maximum capacitance values to a silicon compiler for automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values;

whereby said maximum capacitance values for said integrated circuit are automatically adjusted so as to reduce the difficulty of routing connections between said integrated circuit'"'"'s components.

5. The computer aided design system set forth in claim 4, each said node having a fanout value corresponding to the number of said component inputs ports coupled to said node;

wherein said routing difficulty function means computes a routing difficulty value which is a predefined function of said maximum capacitance value for a corresponding node and said fanout value of said node.

6. The computer aided design system set forth in claim 4, wherein said optimization means first selects components coupled to said output nodes of said integrated circuit and progresses toward components adjacent said input nodes.

7. A method of synthesizing an integrated circuit, the steps of the method comprising:

receiving and storing in a computer memory a netlist which specifies an integrated circuit by denoting a list of components in said integrated circuit and a set of nodes interconnecting said components;

each said component of said integrated circuit having at least one input port and at least one output port;

assigning a time delay value and a corresponding initial maximum capacitance value to each said node, wherein said assigned values are consistent with a predefined set of timing constraints on said integrated circuit'"'"'s operation;

computing a routing difficulty value for said integrated circuit, said routing difficulty value comprising a predefined function of the said maximum capacitance values for said nodes;

for each of at least of a plurality of components in said integrated circuit;

decreasing said maximum capacitance value for at least one of said component'"'"'s output nodes and increasing by a corresponding amount said maximum capacitance value for at least one node coupled to an input port of said component;

said changes in said maximum capacitance values being retained only when said changes decrease said computed routing difficulty value; and

passing said netlist and maximum capacitance values to a silicon compiler for automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values.

8. A method of synthesizing an integrated circuit, the steps of the method comprising:

receiving and storing in a computer memory a netlist which specifies an integrated circuit by denoting a list of components in said integrated circuit and a set of nodes interconnecting said components;

each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit;

each said node being coupled to a number of said components;

providing a set of timing constraints for propagation of signals from specified ones of said circuit input nodes to specified ones of said circuit output nodes;

defining a set of signal delays associated with said components denoted in said netlist;

assigning a time delay value and a corresponding initial maximum capacitance value to each said node, wherein said assigned values are consistent with said set of timing constraints;

computing a routing difficulty value, comprising a sum of routing difficulty values associated with all of said nodes in said integrated circuit, each said routing difficulty value comprising a predefined function of the said maximum capacitance value for a corresponding node and said number of integrated circuit components coupled to said node;

repeating the following steps until changes in said computed routing difficulty value meet predefined criteria;

for each component in said integrated circuit, beginning with components coupled to said output nodes and progressing toward components adjacent said input nodes;

decreasing said time delay associated with a node coupled to an output port of said component by decreasing said maximum capacitance value for at least one of said component'"'"'s output nodes and increasing by a corresponding amount said maximum capacitance value for at least one node coupled to an input port of said component;

said changes in said maximum capacitance values being retained only when said changes decrease said computed routing difficulty value; and

passing said netlist and maximum capacitance values to a silicon compiler for automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values.