Reporting delayed coprocessor exceptions to code threads having caused the exceptions by saving and restoring exception state during code thread switching

• US 5,197,138 A
• Filed: 12/26/1989
• Issued: 03/23/1993
• Est. Priority Date: 12/26/1989
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Huang, Hai, Hobbs, Steven O.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): SHAH, ALPESH
• Application Number:
  US07/457,144
• Time in Patent Office: 1,183 Days
• Field of Search: 395/375, 395/800
• US Class Current: 712/222
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/463 Program control block organisation
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

Save-Exception-State and Restore-Exception-State primitives are defined in the operating system and are used to confine the reporting of delayed asynchronous coprocessor exceptions to the respective code threads that generate the exceptions. The Save-Exception-State primitive saves the coprocessor exception state pertinent to the currently executed code thread, and the Restore-Exception-State primitive restores a selected one of the exception states having been saved. The Save-Exception-State primitive synchronizes the coprocessor, disables use of the coprocessor, saves any pending coprocessor exception state into memory, and clears the coprocessor exception state information from the coprocessor or a "thread descriptor" area of memory allocated to the current code thread. The Restore-Exception-State primitive synchronizes the coprocessor, disables use of the coprocessor, reports any pending exceptions in the coprocessor, and restores the saved exception state into a respective code thread descriptor in memory allocated to the code thread having generated the saved exception state information. The restored exception state is reported by a "Coprocessor-Disabled" exception handler that checks for any exceptions pending in the coprocessor or thread descriptor, when necessary stores the coprocessor state information from the process which last executed a coprocessor instruction, when necessary retrieves the coprocessor state information for the current process, reports any pending exceptions, and reenables use of the coprocessor.

Claims

1. A method for handling a delayed exception generated by a coprocessor in a data processing system, said data processing system also including a main processor that issues instructions to said coprocessor, said coprocessor being capable of operating on an asynchronous basis with respect to said main processor such that the coprocessor executes issued instructions simultaneously while the main processor executes further instructions, said method comprising the steps of:

(a) operating said main processor and said coprocessor on said asynchronous basis to execute instructions in a first code thread including an instruction that, when executed, causes said coprocessor to generate said delayed exception; and

then

(b) synchronizing the coprocessor with the main processor such that the main processor does not process any further instructions until all instructions have been issued to the coprocessor are guaranteed to complete without causing additional exceptions; and

then

(c) saving a pending state of said delayed exception into memory; and

then

(d) clearing said coprocessor of the state of said delayed exception; and

then

(e) operating said main processor and said coprocessor on said asynchronous basis to execute a second code thread; and

then

(f) again synchronizing said coprocessor with said main processor; and

then

(g) disabling the use of said coprocessor; and

then

(h) operating the main processor to execute instructions in said first code thread until a coprocessor disabled exception occurs when said main processor issues an instruction to the disabled coprocessor; and

then

(i) reporting to said first code thread the presence of the pending state of said delayed exception having been saved in memory; and

then

(j) enabling said coprocessor; and

then

(k) again operating said main processor and said coprocessor on said asynchronous basis to execute instructions in said first code thread.

2. The method as claimed in claim 1, wherein the coprocessor includes means for executing vector instructions.

3. The method as claimed in claim 2, wherein the delayed exception is a vector arithmetic exception.

4. A method for handling a delayed exception generated by a coprocessor in a data processing system, said data processing system also including a main processor that issues instructions to said coprocessor, said coprocessor being capable of operating on an asynchronous basis with respect to said main processor such that the coprocessor executes issued instructions simultaneously while the main processor executes further instructions, said method comprising the steps of:

(a) operating said main processor and said coprocessor on said asynchronous basis to execute instructions in a first code thread including an instruction that, when executed, causes said coprocessor to generate said delayed exception; and

then

(b) disabling the use of said coprocessor; and

then

(c) operating said main processor to execute instructions in at least a second code thread until a coprocessor disabled exception occurs when said main processor issues an instruction to the disabled coprocessor; and

then

(d) synchronizing the coprocessor with the main processor such that the main processor does not process any further instructions until all instructions having been issued to the coprocessor are guaranteed to complete without causing additional exceptions; and

the

(e) saving a pending state of said delayed exception from the first code thread into memory allocated to said first code thread; and

then

(f) clearing said coprocessor of the state of said delayed exception; and

then

(g) operating said main processor and said coprocessor on said asynchronous basis to execute instructions in the second code thread; and

then

(h) disabling the use of said coprocessor; and

then

(i) operating said main processor to execute instructions in said first code thread until a coprocessor disabled exception occurs when said main processor issues an instruction to the disabled coprocessor; and

then

(j) reporting to said first code thread the presence of the pending state of said delayed exception having been saved in memory; and

then

(k) enabling said coprocessor; and

then

(l) again operating said main processor and said coprocessor on said asynchronous basis to execute instructions in said first code thread.

5. The method as claimed in claim 4, wherein the coprocessor includes means for executing vector instructions.

6. The method as claimed in claim 5, wherein said delayed exception is a vector arithmetic exception.

7. A method for saving exception state information about delayed exceptions having been generated by a coprocessor in a data processing system during execution of instructions in a code thread, said coprocessor having a register for holding the exception state information, said data processing system also including a memory for receiving and holding the exception state information from said register, and a main processor that issues instructions to said coprocessor, said coprocessor being capable of operating on an asynchronous basis with respect to said main processor such that the coprocessor executes issued instructions simultaneously while the main processor executes further instructions, said method comprising the steps of:

(a) operating said main processor and said coprocessor on said asynchronous basis to execute instructions in said code thread; and

then

(b) synchronizing the coprocessor with the main processor such that the main processor does not process any further instructions of said code thread until all instructions having been issued to the coprocessor are guaranteed to complete without causing additional exceptions; and

(c) upon completion of said synchronizing of the coprocessor with the main processor,

(i) checking whether the exception state information held in said register indicates a pending exception having been generated by execution of at least one of said instructions in said code thread, and when a pending exception is so indicated, transferring the exception state information from said register to a save area of said memory, and clearing the exception state information from said register; and

(ii) checking whether exception state information held in a thread descriptor area of said memory allocated to said code thread indicates a pending exception having been generated by execution by said coprocessor of at least one of said instructions in said code thread, and when a pending exception is so indicated, transferring that exception state information from said thread descriptor area of said memory to said save area of said memory, and clearing that exception state information from said thread descriptor area of said memory.

8. The method as claimed in claim 7, wherein the coprocessor includes means for executing vector instructions.

9. The method as claimed in claim 8, wherein the exceptions include vector arithmetic exceptions.

10. A method for reporting delayed exceptions having been generated by a coprocessor in a data processing system during execution of instructions in a code thread, said data processing system also including a main processor that issues instructions to said coprocessor, said coprocessor being capable of operating on an asynchronous basis with respect to said main processor such that the coprocessor executes issued instructions simultaneously while the main processor executes further instructions, said method comprising the steps of:

(a) disabling said coprocessor;

(b) when said coprocessor is disabled, operating the main processor to execute instructions in said code thread until a coprocessor disabled exception occurs when said main processor issues an instruction to the disabled coprocessor;

(c) in response to said coprocessor disabled exception,

(i) checking whether exception state information saved in thread descriptor memory allocated to said code thread indicates a pending exception, and when a pending exception is so indicated, reporting the presence of the pending exception to said code thread and clearing the exception state information saved in the thread descriptor memory;

(ii) checking whether exception state information held in a coprocessor register indicates a pending exception, and when a pending exception is so indicated, reporting the presence of the pending exception to said code thread and clearing said coprocessor register; and

(iii) enabling said coprocessor.

11. The method as claimed in claim 10, wherein the coprocessor includes means for executing vector instructions.

12. The method as claimed in claim 11, wherein the exceptions include vector arithmetic exceptions.

13. A method for restoring saved state information about a delayed exception having been generated by a coprocessor in a data processing system while executing instructions in a first code thread, said data processing system also including a main processor that issues instructions to said coprocessor, said coprocessor being capable of operating on an asynchronous basis with respect to said main processor such that the coprocessor executes issued instructions simultaneously while the main processor executes further instructions, said method comprising the steps of:

(a) synchronizing the coprocessor with the main processor such that the main processor does not process any further instructions in a second code thread until all instructions having been issued to the coprocessor are guaranteed to complete without causing additional exceptions; and

(b) after the coprocessor has been synchronized with the main processor;

(i) disabling the use of said coprocessor;

(ii) checking whether exception state information in the coprocessor indicates a pending exception, and when a pending exception is so indicated, reporting the presence of said pending exception to said second code thread and clearing the exception state information in the coprocessor;

(iii) checking whether a coprocessor exception is indicated by exception state information in a thread descriptor area of memory allocated to said first code thread, and when an exception is so indicated, reporting the presence of the pending exception to said first code thread and clearing the exception state information in the thread descriptor; and

(iv) moving saved state information about said delayed exception from a save area of memory into a thread descriptor area of memory allocated to said first code thread.

14. The method as claimed in claim 13, wherein the coprocessor includes means for executing vector instructions.

15. The method as claimed in claim 14, wherein said delayed exception is a vector arithmetic exception.

16. A method for reporting saved state information about a delayed exception having been generated by a coprocessor in a data processing system during execution of a code thread, said data processing system also including a main processor that issues instructions to said coprocessor, said coprocessor being capable of operating on an asynchronous basis with respect to said main processor such that the coprocessor executes issued instructions simultaneously while the main processor executes further instructions, said method comprising the steps of:

(a) operating the main processor, with the coprocessor disabled, to execute instructions in said code thread until a coprocessor disabled exception occurs when the main processor issues an instruction to the disabled coprocessor; and

(b) then checking whether exception state information in code thread descriptor memory allocated to said code thread indicates that said delayed exception is pending, and when said delayed exception is so indicated, reporting to said code thread that said delayed exception is pending.

17. The method as claimed in claim 16, wherein the coprocessor includes means for executing vector instructions.

18. The method as claimed in claim 17, wherein the delayed exception is a vector arithmetic exception.

19. A method of operating a data processing system including a coprocessor and a main processor that issues instructions to said coprocessor, said coprocessor being capable of operating on an asynchronous basis with respect to said main processor such that the coprocessor executes issued instructions simultaneously while the main processor executes further instructions, said coprocessor generating exceptions during the asynchronous operation, the exceptions being indicated by exception state information held in said coprocessor, said method comprising the steps of:

(a) allocating respective thread descriptor memory locations to code threads including the instructions executed by the coprocessor and the main processor;

(b) operating said coprocessor on said asynchronous basis with respect to said main processor;

(c) identifying one of said code threads as a coprocessor-owner code thread which includes instructions that were last executed by said coprocessor;

(d) identifying a current code thread having instructions that are currently being executed by said main processor; and

(e) saving exception state information pertaining to said current code thread by;

(1) checking whether the current code thread is also the coprocessor-owner code thread; and

when it is, synchronizing the coprocessor with the main processor such that the main processor does not process any further instructions until all instructions having been issued to the coprocessor are guaranteed to complete without causing additional exceptions, and then checking whether an exception is indicated by the exception state information held in the coprocessor, and when an exception is so indicated, transferring the exception state information to a respective save area of memory and clearing the exception indication from the exception state information held in the coprocessor; and

(2) checking whether exception state information held in the thread descriptor memory allocated to the current code thread indicates a coprocessor exception pertinent to the current code thread; and

when such an exception is so indicated, transferring that exception state information from the thread descriptor memory allocated to the current code thread to said save area of memory and clearing that exception indication form the exception state information held in the thread descriptor memory allocated to the current code thread;

wherein said steps (c), (d) and (e) are repeated during the execution of a plurality of code threads.

20. The method of operating the data processing system as claimed in claim 19, further comprising a step (f) of restoring the exception state information saved in said save area of memory by:

(1) identifying a respective code thread to have its saved exception state information restored;

(2) checking whether said respective code thread is the coprocessor-owner code thread; and

when it is, synchronizing the coprocessor with the main processor such that the main processor does not process any further instructions until all instructions having been issued to the coprocessor are guaranteed to complete without causing additional exceptions, then checking whether an exception is indicated by the exception state information held in the coprocessor, and when an exception is so indicated, reporting and clearing the exception indication from the exception state information held in the coprocessor;

(3) checking whether a coprocessor exception is indicated by exception state information held in the thread descriptor memory allocated to said respective code thread, and when an exception is so indicated, reporting the exception indication to said respective code thread form the exception sate information held in the thread descriptor memory allocated to said respective code thread and clearing the exception indication from the exception state information held in the thread descriptor memory allocated to said respective code thread; and

(4) transferring the saved exception state information for said respective code thread from said save area to the thread descriptor memory allocated to said respective code thread.

21. The method of operating the data processing system as claimed in claim 20, further comprising disabling the coprocessor after it is synchronized in each of steps (e)(1) and (f)(2), and further comprising the step (g) of reporting a coprocessor exception for the coprocessor-owner code thread to said coprocessor-owner code thread when the main processor issues a coprocessor instruction and the coprocessor is disabled, the coprocessor exception being reported by:

(1) checking whether an exception is indicated by the exception state information held in the coprocessor, and when an exception is so indicated, reporting and clearing the exception indication from the exception state information held in the coprocessor;

(2) checking whether a coprocessor exception is indicated by exception state information in the thread descriptor memory allocated to the coprocessor-owner code thread, and when an exception is so indicated, reporting the exception indication to said coprocessor-owner code thread from the exception state information in the thread descriptor memory allocated tot he coprocessor-owner code thread and clearing the exception indication from the exception state information in the thread descriptor memory allocated to the coprocessor-owner code thread.

22. A data processing system comprising:

(a) a main processor including means for executing instructions, wherein said mean for executing instruction includes means for issuing coprocessor instructions;

(b) a coprocessor coupled to said main processor to receive the issued coprocessor instructions, said coprocessor including means for executing said coprocessor instructions on an asynchronous basis with respect to said main processor such that the coprocessor executes issued coprocessor instructions simultaneously while the main processor executes further instructions;

said means for executing coprocessor instructions including means for generating coprocessor exceptions; and

coprocessor further including means for disabling execution of further issued coprocessor instructions in response to a coprocessor exception, and means for transmitting to said main processor a coprocessor disabled fault signal upon receipt of a coprocessor instruction issued form said main processor when execution of further issued coprocessor instructions is disabled;

said coprocessor being coupled to said main processor for transmission of said disabled fault signal from said coprocessor to said main processor and for permitting said main processor to read exception state information from said coprocessor;

wherein said main processor includes exception reporting means for reporting said exception state information to a code thread having an instruction having caused said exception to be generated when said instruction is executed by said coprocessor, said exception reporting means including;

(i) disabled fault processing means responsive to said disabled fault signal for reporting said exception information to said code thread from a thread descriptor area of memory allocated to said code thread when said exception is indicated in said thread descriptor during execution of said code thread by said main processor, and when said exception information is not indicated in said thread descriptor area of memory during execution of said code thread by said main processor, reporting said exception information by reading said exception information from said coprocessor.

23. The data processor as claimed in claim 22, wherein said main processor includes exception state saving means for saving in memory said exception state read from said coprocessor, and said exception state saving means includes means for synchronizing said coprocessor with said main processor such that said main processor does not process any further instructions until all instructions having been issued to the coprocessor are guaranteed to complete without causing a subsequent exception, disabling use of said coprocessor after said coprocessor is synchronized with said main processor, saving pending exception state of the disabled coprocessor into said memory, and clearing the pending exception state from the disabled coprocessor.

24. The data processor as claimed in claim 23, wherein said exception state saving means includes means for clearing coprocessor exception state information from a thread descriptor area of memory allocated to a currently executed code thread.

25. The data processor as claimed in claim 23, wherein said main processor includes exception state restoring means for synchronizing said coprocessor with said main processor such that said main processor does not process any further instructions until all instructions having been issued to the coprocessor are guaranteed to complete without causing a subsequent exception, disabling use of said coprocessor after said coprocessor is synchronized with said main processor, reporting any pending exception in said coprocessor to a code thread having generated the pending exception in said coprocessor, and restoring saved exception state in memory into a thread descriptor area of memory allocated to a code thread having generated said saved exception state in memory.