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Sliced addressing multi-processor and method of operation

  • US 5,197,140 A
  • Filed: 11/17/1989
  • Issued: 03/23/1993
  • Est. Priority Date: 11/17/1989
  • Status: Expired due to Term
First Claim
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1. A multi-processing system comprising:

  • m memories, each memory having a unique addressable space, said unique addressable spaces of said m memories being adjacent with the total addressable space of said m memories defined by a single address word having n bits;

    addition circuitry for generating a next address word for access to said m memories from said single address word and an index value, said addition circuitry includingn one bit adder circuits disposed in order from a least significant bit to a most significant bit, each of said one bit adder circuit having a first input for receiving a corresponding bit of said single address word, a second input for receiving a corresponding bit of said index value, a carry-out output, a carry-in input, and a resultant output, the resultant outputs of said n one bit adder circuits forming corresponding bits of said next address wordn multiplex circuits, one said multiplex circuit associated with each said one bit adder circuit, each said multiplex circuit having two inputs and a single output, one of said inputs connected to said carry-out output of said associated one bit adder circuit, the other of said inputs connected to said carry-in input of said associated one bit adder circuit and said output connected to the carry-in input of the next most significant one bit adder circuit.

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