Sliced addressing multi-processor and method of operation

• US 5,197,140 A
• Filed: 11/17/1989
• Issued: 03/23/1993
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Balmer, Keith
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): WHITFIELD, MICHAEL
• Application Number:
  US07/437,946
• Time in Patent Office: 1,222 Days
• Field of Search: 395/400, 395/800, 395/163, 395/166, 364/749, 364/786, 364/787
• US Class Current: 711/220
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. An addressing scheme, called sliced addressing, is used to spread contiguous related data over several memories so that the data can be concurrently accessed by several processors. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Claims

1. A multi-processing system comprising:

m memories, each memory having a unique addressable space, said unique addressable spaces of said m memories being adjacent with the total addressable space of said m memories defined by a single address word having n bits;

addition circuitry for generating a next address word for access to said m memories from said single address word and an index value, said addition circuitry including

n one bit adder circuits disposed in order from a least significant bit to a most significant bit, each of said one bit adder circuit having a first input for receiving a corresponding bit of said single address word, a second input for receiving a corresponding bit of said index value, a carry-out output, a carry-in input, and a resultant output, the resultant outputs of said n one bit adder circuits forming corresponding bits of said next address word

n multiplex circuits, one said multiplex circuit associated with each said one bit adder circuit, each said multiplex circuit having two inputs and a single output, one of said inputs connected to said carry-out output of said associated one bit adder circuit, the other of said inputs connected to said carry-in input of said associated one bit adder circuit and said output connected to the carry-in input of the next most significant one bit adder circuit.

2. The system set forth in claim 1 wherein each multiplex circuit further includes a control input for selecting which of said input of said multiplex circuit is connected to said output of said multiplex circuit.

3. The system set forth in claim 2 wherein each said one bit adder circuit includes an inhibit input connected to said control input of said associated multiplex circuit for inhibiting the addition function of said one bit adder circuit upon selection of connecting said carry-in input of said one bit adder circuit to said carry-in input of said next most significant one bit adder circuit.

4. The system set forth in claim 1 wherein said index value is one.

5. An addressing system for storing contiguous data in either a single memory or sliced across several memories, said data stored in said memory or memories under control of a multi-bit address word, said system comprising:

an adder circuit for accepting said address word and an index value to be added to said address word to specify a next address word, said adder circuit having a plurality of adder circuit bit positions disposed in order from a least significant bit position to a most significant bit position, wherein said adder circuit bit positions each have a carry-out and a carry-in input; and

a plurality of multiplex circuits, one multiplex circuit associated with each said adder circuit bit position, each said multiplex circuit having two inputs and an output, one of said inputs connected to said carry-out output of said associated adder circuit bit position, the other of said inputs connected to said carry-in input of said associated adder circuit bit position, and said output connected to the carry-in input of the next most significant adder circuit bit position.

6. The addressing system set forth in claim 5 wherein each multiplex circuit further includes a control input for selecting which of said inputs of said multiplex circuit is connected to said output of said multiplex circuit.

7. The addressing system set forth in claim 5 wherein each said adder circuit bit position includes an inhibit input connected to said control input of said associated multiplex circuit for inhibiting the addition function of said adder circuit bit position upon selection of connecting said carry-in input of said adder circuit bit position to said carry-in input of said next most significant one bit adder circuit.

8. The addressing system set forth in claim 5 wherein said index value is one.

9. A multiprocessor system comprising:

a first memory for storing data in a first address space;

a plurality of second memories, each second memory having a unique second address space, said unique second address spaces of said second memories being adjacent whereby the total address space of said second memories is defined by a second address word having n bits;

a plurality of processors, each processor capable of at least one memory access of one of said second memories per memory cycle;

a transfer processor connected to said first memory and said second memories for transferring data therebetween, said address processor including

means for generating a consecutive first address words corresponding to predetermined consecutive addresses of said first address space of said first memory;

means for generating a second address word for specifying an address within said second address space within said plurality of said second memories from a prior second address word and an index value, said means for generating a second address word including

means for specifying a slice mask on n bits indicating a block of bits for carry skipping;

n one bit adder circuits disposed in order from a least significant bit to a most significant bit, each of said one bit adder circuits having a first input for receiving a corresponding bit of said prior second address word, a second input for receiving a corresponding bit of said index value, a inhibit input connected to a corresponding bit of said slice mask, a carry-in input, a resultant output and a carry-out output, each one bit adder circuit generating (a) a resultant output and carry-out output corresponding to said first and second inputs and said carry-in input when not inhibited by said corresponding bit of said slice mask, and (b) a resultant output equal to said first input and a zero carry-out when inhibited by said corresponding bit of said slice mask;

n multiplex circuits, one multiplex circuit associated with each one bit adder circuit, each multiplex circuit having a first input connected to said carry-out output of said associated one bit adder circuit, a second input connected to said carry-in input of said associated one bit adder circuit, a control input connected to a corresponding bit of said slice mask and an output connected to the carry-in input of the next most significant one bit adder circuit, each multiplex circuit connecting (a) said second input to said output when said corresponding bit of said slice mask does not inhibit said associated one bit adder circuit, and (b) said first input to said output when said corresponding bit of said slice mask inhibits said associated one bit adder circuit.

10. The multiprocessor system of claim 9, wherein said index value is one.

11. The multiprocessor system of claim 9, wherein said transfer processor employs each first address word to recall data from said first memory and employs each second address word to store data in a corresponding second memory.

12. The multiprocessor of claim 9, wherein said transfer processor employs each second address word to recall data from a corresponding second memory and employs each first address word to store data in said first memory.

13. The multiprocessor of claim 9, wherein said plurality of second memories, said plurality of processors and said transfer processor are all disposed on a single integrated circuit.