Method of highly compact EPROM and flash EEPROM devices

• US 5,198,380 A
• Filed: 07/17/1989
• Issued: 03/30/1993
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Trinh, Loc Q.
• Application Number:
  US07/381,139
• Time in Patent Office: 1,352 Days
• Field of Search: 437/43, 437/44, 437/52, 437/49, 437/48, 357/23.5, 365/185, 156/657
• US Class Current: 438/257
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. A method of forming a split-channel electrically programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:

forming on said surface a floating gate having a first pair of opposite sidewalls across said floating gate in a first direction and a second pair of opposite sidewalls across said floating gate in a second direction, said first and second directions being substantially perpendicular to each other, said second pair of sidewalls being substantially parallel to each other and separated by a first distance, and said floating gate being electrically isolated by a gate dielectric layer from said substrate,

forming a spacer having one edge immediately adjacent only one of said first pair of sidewalls of said floating gate and an opposite edge of said spacer being positioned a distance therefrom over said substrate surface that is defined by an etching process without the use of a separate mask,

forming source and drain regions in said substrate by using the adjacent floating gate and spacer as a channel mask, whereby a channel region is formed in the substrate under the masked region between the source and drain regions,

thereafter removing said spacer,

thereafter forming a control gate extending in said first direction over at least a portion of the floating gate and substrate channel region that was occupied by said spacer, said control gate being electrically insulated from said floating gate and said substrate,

forming regions of a tunnel erase dielectric layer on each of said second pair of floating gate sidewalls, and

forming on the tunnel dielectric layers a pair of parallel erase gates extending in said first direction between the source and drain regions and separated in said second direction by a second distance that is less than said first distance,

whereby a split-channel electrically programmable read only memory transistor is formed.

2. The method according to claim 1 wherein the step of forming a spacer immediately adjacent only one sidewall of the floating gate includes the steps of:

depositing a layer of material over said floating gate and extending a distance beyond said floating gate sidewalls,

anisotropically etching said layer of material for a time to remove it except for first and second portions immediately adjacent opposite sidewalls of said floating gate, and

selectively removing said first portion of material without removal of said second portion, whereby said second portion remains as said spacer.

3. The method according to claim 1 wherein the step of forming a spacer immediately adjacent only one sidewall of the floating gate includes the steps of:

depositing a thin layer of protective material over said floating gate and extending a distance beyond said floating gate sidewalls,

depositing a relatively thick layer of spacer material over said thin layer and extending a distance beyond said floating gate sidewalls,

anisotropically etching said layer of spacer material for a controlled time to remove it except for first and second portions immediately adjacent opposite sidewalls of said floating gate, said first portion also being positioned adjacent the location of said drain region and said second portion being positioned adjacent the location of said source region, and

selectively removing said first portion of material without removal of either one of said second portion and said protective material layer, whereby said second portion remains as said spacer.

4. The method according to claim 2 wherein the step of selectively removing said first portion of material includes the steps of:

covering with a masking layer an area including said second portion of material but not said first portion,

etching away said first portion of material, and

removing said masking layer.

5. The method according to claim 1 wherein each of the steps of forming a floating gate, forming a control gate and forming a pair of erase gates include forming their respective gates in a conductive layer that is different from the others.

6. The method according to claim 1 comprising the additional step of forming a second dielectric to insulate the pair of erase gates from said control gate.

7. The method according to claim 6 wherein the step of forming the control gate includes forming said control gate to extend over only a portion of said floating gate in a manner leaving portions of said floating gate adjacent said second pair of sidewalls that is not covered by the control gate, and wherein the step of forming an erase dielectric layer includes the step of forming said layer over the portion of the floating gate not covered by the control gate without forming said layer over a portion of the floating gate over which the control gate extends.

8. The method according to claim 7 wherein the steps of forming the tunnel erase dielectric layer and the erase gates are carried out prior to the steps of forming the second dielectric layer and the control gate.

9. The method according to claim 1 wherein the step of forming a region of a tunnel erase dielectric layer on each of said second pair of said floating gate sidewalls includes forming the layers on a top surface of the floating gate adjacent the second pair of sidewalls, and wherein the step of forming a pair of parallel erase gates includes the step of forming each erase gate over said floating gate top surface with one of the tunnel dielectric layers therebetween.

10. The method according to claim 1 wherein the step of forming a region of a tunnel erase dielectric layer on each of the second pair of sidewalls of said floating gate includes forming the layers along said sidewalls substantially without being formed on the floating gate top surface, and wherein the step of forming a pair of parallel erase gates includes the step of forming each gate adjacent one of said sidewalls with one of the tunnel dielectric layers therebetween.

11. The method according to claim 10 which includes an additional step of forming a thin layer of dielectric on said substrate between said source and drain regions on at least portions of the substrate over which the erase gates are positioned, and wherein the step of forming the erase gates includes forming said erase gates over said thin dielectric layer, whereby said erase gates are capacitively coupled to said substrate in order to provide isolation of said cell in said second direction.

12. A method of forming a split-channel flash electrically erasable and programmable read only memory cell on a semiconductor substrate surface, comprising the steps of:

forming on said surface a floating gate having opposite sides in a first direction across said floating gate and opposite ends in a second direction across said floating gate and separated by a first distance, said first and second directions being substantially orthogonal to each other, said floating gate being electrically insulated from said substrate by a gate dielectric layer,

forming in said substrate a drain region adjacent one side of said floating gate and a source region spaced apart from an opposite side of said floating gate, thereby to form a channel region between the source and drain that has a first channel region under the floating gate and a second channel region between the source region and the opposite floating gate side,

forming a control gate extending in said first direction over at least a portion of the floating gate and said second channel region, said control gate being electrically insulated from said floating gate and said substrate,

forming regions of a tunnel erase dielectric layer on each of opposite ends of said floating gate, and

forming a pair of parallel erase gates elongated in said first direction and extending between the source and drain regions and across the opposite ends of the floating gate on the tunnel dielectric layer, said erase gates being separated in said second direction by a second distance, said second distance being less than said first distance.

13. The method according to claim 12 wherein the step of forming the control gate includes forming said control gate to extend over said floating gate in a manner to leave surface areas portions of the floating gate adjacent each of its said opposite ends not covered by the control gate, and wherein the step of forming an erase dielectric layer includes the step of forming said layer over said surface area portions of the floating gate not covered by the control gate, whereby said erase gates overlie said floating gate surface area portions with the tunnel dielectric layer therebetween.

14. The method according to claim 12 wherein the step of forming a region of a tunnel erase dielectric layer on each of opposite ends of said floating gate includes forming the layers on a top surface of the floating gate, and wherein the step of forming a pair of parallel erase gates includes the step of forming each gate over said top surface with at least one of the tunnel dielectric layers therebetween.

15. The method according to claim 12 wherein the step of forming a region of a tunnel erase dielectric layer on each of opposite ends of said floating gate includes forming the layers along opposite sidewalls thereof, and wherein the step of forming a pair of parallel erase gates includes the step of forming each gate adjacent one of said sidewalls with one of the tunnel dielectric layers therebetween.

16. The method according to any one of claims 12-15 which includes an additional step of forming a thin layer of gate dielectric on said substrate between said source and drain regions on at least portions of the substrate over which the erase gates are positioned, and wherein the step of forming the erase gates includes forming said erase gates over said thin dielectric layer, whereby said erase gates are capacitively coupled to said substrate in order to provide isolation of said cell in said second direction.

17. The method according to claim 15 wherein the step of forming the floating gate includes forming its said opposite ends to each terminate in a single sharp edge that is thinner than a body of said floating gate and intermediate of top and bottom surfaces thereof.

22. The method according to claim 16 wherein the step of forming the floating gates includes the step of texturing said floating gate end walls in order to enhance the tunnel conduction properties of said tunnel erase dielectric layer adjacent said end walls.

18. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:

forming on said substrate a plurality of rectangularly shaped floating gates in a two dimensional array of symmetrical rows and columns by use of a first photolithography mask, each floating gate being isolated from said substrate by a gate dielectric layer and having opposing substantially parallel end walls separated by a first distance in a first direction,

forming source and drain regions spaced apart in said substrate with a channel therebetween,

forming a tunnel erase dielectric layer on the floating gates in regions adjacent their opposing ends,

forming a plurality of substantially parallel control gates that each extend in a second direction over several of the floating gates with insulation therebetween, said first and second directions being substantially perpendicular to each other, and

forming on said substrate with a second photolithography mask separate from said first mask a plurality of substantially parallel erase gates elongated in said second direction and separated by a second distance in said first direction and positioned between rows of floating gates with a width sufficient to contact said erase dielectric regions on the floating gates thereof, said second distance being less than said first distance.

19. The method according to claim 18 wherein the step of forming the tunnel dielectric layer includes forming said regions on a top surface of the floating gates adjacent their said opposing end walls, whereby the total area of said tunnel erase regions of overlap is determined by the difference between said first and second predetermined dimensions and is insensitive to misalignment between the first and second masks.

20. The method according to claim 18 wherein the step of forming the tunnel dielectric layer includes forming said regions on said floating gate opposing end walls, thereby to provide for the erase gates to contact said tunnel dielectric layer regions even if the first and second masks are misaligned.

21. The method according to claim 18 wherein the step of forming the erase gates includes forming said erase gates on a thin gate oxide on the substrate.

23. The method according to claim 18 wherein the step of forming the floating gates additionally includes the step of oxidizing the gates in order to form sharp tips at their said opposing end walls.

24. The method according to claim 18 wherein the step of forming the floating gates includes forming said floating gates to have a thickness of less than 200 nanometers.

25. The method according to claim 18 wherein the step of forming the floating gates includes the step of shaping the edges of said floating gates so as to have sharp tips.

26. The method according to claim 18 wherein the step of forming the source and drain regions comprises the steps of:

including as part of said another mask a spacer having one edge positioned immediately adjacent said floating gate and an opposite edge position defined by an etching process without the use of a mask, and

removing said spacer after the source region has been formed, thereby to define the position of the source regions relative to the floating gates.

27. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:

forming on said substrate a plurality of rectangularly shaped floating gates in a two dimensional array of symmetrical rows and columns by use of a first mask, each floating gate being isolated from said substrate by a gate dielectric layer and having opposing ends separated by a first distance,

forming source and drain regions in said substrate by using the plurality of floating gates as a portion of a second mask to define a channel between the source and drain regions, wherein each of said channels has a first channel portion adjacent to said drain region and covered by said floating gate and a second channel portion adjacent to said source region,

forming a tunnel erase dielectric layer on the surface of said floating gates,

forming on said substrate with a third mask a plurality of elongated parallel erase gates separated by a second distance smaller than said first distance and positioned between adjacent rows of floating gates in the direction extending between said source and drain regions, said erase gates having a width sufficient to contact on opposite sides thereof said tunnel erase dielectric layers of the erase gates at said opposing end of the floating gates thereof,

replacing said tunnel erase dielectric layer on the surface of said floating gates which is not covered by said erase gates and on the surface of said substrate which is not covered by said floating gate and said erase gate with a second dielectric layer, said second dielectric layer also forming an insulation layer over said erase gates, and

forming by a fourth mask a plurality of elongated parallel control gates in between each pair of said erase gates and extending in the same direction as said erase gates such that each control gate extends over several of the floating gates and their adjacent second channel portions, said control gates being insulated by said second dielectric layer from said floating gates, said second channel portion, and said erase gates.

28. The method according to claim 27 wherein the step of forming the tunnel erase dielectric layer includes doing so over the top surface and sidewalls of the floating gates adjacent said opposing ends, whereby at least one of the erase gates overlays a top surface area of a floating gates even if the first and third masks are misaligned.

29. The method according to claim 27 wherein the step of forming the source and drain regions comprises the steps of:

including as part of said second mask a spacer having one edge positioned immediately adjacent said floating gate and an opposite edge position defined by an etching process without the use of a mask, thereby forming said spacer over said second channel portion, and

removing said spacer after the source region has been formed, thereby to define the position of the source and second channel portion.

30. The method according to claim 27 wherein each of said first channel portions includes a short channel region adjacent to said drain region which is more heavily doped than the rest of said channel,

said short channel region formed by implanting dopant into an area of said channel which is defined by using a controlled sideways etching of a masking layer to remove said masking layer over said short channel region but not remove it from the remaining part of said channel.

31. The method according to claim 27 wherein the step of forming the floating gates includes forming the floating gates so as to overly the gate dielectric layer of said first channel portion for substantially the entire said first distance between said opposing ends thereof, thereby defining the channel width of said first channel portion to be substantially the same as said first distance.

32. The method according to claim 27 which comprises the additional step of forming a thin dielectric layer in the substrate regions between adjacent rows of floating gates prior to the step of forming the erase gates, and wherein the erase gates are formed over said thin dielectric layer.

33. The method according to claim 27 wherein the area of overlap between said floating gate and said control gate and the area of overlap between said floating gate and said erase gates are chosen so as to provide a first capacitive coupling between said floating gate and said erase gates and a second capacitive coupling between said floating gate and said control gate, said first capacitive coupling being significantly less than said second capacitive coupling

34. The method according to claim 27 wherein the thicknesses and dielectric constants of said gate dielectric layer, said tunnel erase dielectric, and said second dielectric layer are chosen to provide a first capacitive coupling between said floating gate and said erase gates and to provide a second capacitive coupling between said floating gate and said control gate and said substrate, said first capacitive coupling being significantly less than said second capacitive coupling.

35. The method according to claim 27 wherein said first conductive layer is heavily doped polysilicon, said second conductive layer is heavily doped polysilicon, and said third conductive layer is chosen from a group of conductors consisting of polycides, silicides, refractory metals and heavily doped polysilicon.

36. The method according to claim 27 wherein said gate dielectric layer is silicon dioxide, said tunnel erase dielectric is chosen from a group of dielectrics consisting of silicon dioxide, silicon nitride, and a sandwich of thin layers of silicon dioxide and silicon nitride, and said second dielectric layer is chosen from a group of dielectrics comprising silicon dioxide and a sandwich of thin layers of silicon dioxide covered with oxidized silicon nitride.

37. The method according to claim 27 wherein said first conductive layer is a doped polysilicon film which is textured to enhance the tunnel conduction properties of said tunnel erase dielectric.

38. The method according to claim 27 wherein said first conductive layer is a doped polysilicon film having a thickness of less than 200 nanometers.

39. The method according to claim 27 wherein said first conductive layer is a doped polysilicon film whose edges are shaped to have sharp tips.

40. The method according to claim 38 wherein the step of forming the floating gates includes the step of oxidizing the gates in order to form sharp tips at their said opposing ends.

41. A method of forming a two dimensional array of symmetrical rows and columns of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:

forming on said substrate a gate dielectric layer,

forming on said gate dielectric layer by a first mask a plurality of parallel narrow elongated strips in a first conductive layer with their lengths extending in a first direction,

forming source and drain regions in said substrate in elongated narrow strips with their lengths extending in said first direction by using said narrow strips as a portion of a second mask to define channels between said source and drain regions, wherein each such channel between a corresponding one of said source and said drain regions has a first channel portion adjacent to said drain region which is covered by a corresponding one of said narrow strips and a second channel portion adjacent to said source region which is not covered by said narrow strip but adjacent thereto,

forming a second dielectric layer on said first conductive layer and said substrate,

forming with a third mask in a second conductive layer over said second dielectric layer a plurality of parallel strips of elongated control gates having a given width and their lengths extending in a second direction orthogonal to said first direction, thereby to form each control gate extending over several of said narrow strips and said second channel portions,

forming an insulating film over said control gate strips,

removing said second dielectric layer in exposed areas between adjacent strips of said control gates,

removing said narrow strips of said first conductive layer in exposed areas where said second dielectric layer has been removed, thereby forming said first conductive layer into individual floating gates whose opposing ends are essentially self-aligned with the edges of said strips of control gates,

forming a tunnel erase dielectric on the exposed vertical sidewalls of said opposing ends of said floating gates, and

forming with a fourth mask in a third conductive layer a plurality of parallel strips of erase gates in said second direction and overlying said substrate between adjacent rows of floating gates and having a strip to strip separation less than said given width so as to overlie said tunnel erase dielectric on said opposing ends of said floating gates.

42. The method according to claim 41 wherein each of said floating gates overlies said gate dielectric layer over said first channel portion for substantially the entire width between said opposing ends thereof, thereby defining the channel width underneath said floating gate to be essentially the same as said width.

43. The method according to claim 41 wherein the step of forming the source and drain regions comprises the steps of:

including as part of said second mask a spacer having one edge positioned immediately adjacent said floating gate and an opposite edge position defined by an etching process without the use of a mask, thereby forming said spacer over said second channel portion, and

removing said spacer after the source region is formed, thereby to define the position of the source and second channel portion.

44. The method according to claim 41 wherein each of said first channel portions includes a short channel region adjacent to said drain region which is more heavily doped than the rest of said channel, said short channel region being formed by implanting dopant into an area of said channel which is defined by using a controlled sideways etching of a masking layer to remove said masking layer over said short channel region but not remove it from the remaining part of said channel.

45. The method according to claim 41 wherein said erase gates overlie a relatively thin field dielectric layer in the substrate regions between adjacent rows of floating gates.

46. The method according to claim 41 wherein said first conductive layer is heavily doped polysilicon, said second conductive layer is chosen from a group of conductors consisting of polycides, silicides, refractory metals and heavily doped polysilicon, and said third conductive layer is heavily doped polysilicon.

47. The method according to claim 41 wherein said gate dielectric layer is silicon dioxide, said tunnel erase dielectric is chosen from a group of dielectric consisting of silicon dioxide, silicon nitride and a sandwich of thin layers of silicon dioxide and silicon nitride, and said second dielectric layer is chosen from a group of dielectrics comprising silicon dioxide and a sandwich of thin layers of silicon dioxide covered with oxidized silicon nitride.

48. The method according to claim 41 wherein said first conductive layer is a polysilicon film which is textured to enhance the tunnel conduction properties of said tunnel erase dielectric.

49. The method according to claim 41 wherein said first conductive layer is a doped polysilicon film having a thickness of less than 200 nanometers.

50. The method according to claim 41 wherein said first conductive layer is a doped polysilicon film whose edges are shaped to have sharp tips.

51. The method according to claim 49 wherein the step of forming the floating gates includes the step of oxidizing the gates in order to form sharp tips at their said opposing ends.

52. A method of forming an array of split-channel flash electrically programmable read only memory cells on a semiconductor substrate surface, comprising the steps of:

providing a plurality of parallel elongated source and drain regions spaced across the substrate surface, a length of said regions extending in a first direction and being spaced apart to form channel regions therebetween in a second direction, said first and second directions being substantially orthogonal to each other,

forming a two dimensional array of floating gates that are insulated from said substrate surface and spaced apart from each other, said floating gates extending from one of said source and drain regions across the channel region on one side thereof a portion of the distance to an adjacent of the source and drain regions,

providing a plurality of parallel elongated control gates with lengths extending in said second direction over but insulated from a plurality of floating gates and at least a portion of the substrate surface inbetween, said control gates being spaced apart in said first direction, and

providing a plurality of parallel elongated erase gates extending in said second direction and positioned inbetween said control gates in said first direction, said erase gates being capacitively coupled to said floating gates through tunnel dielectric layers and to said substrate surface through thin gate dielectric layers at least across the channel regions in the second direction between source and drain regions and inbetween rows of floating gates in said first direction, whereby adjacent memory cells can be isolated from each other in said first direction by a field effect of the erase gates on the substrate beneath them.