High temperature co-fired ceramic integrated phased array packaging

• US 5,198,824 A
• Filed: 01/17/1992
• Issued: 03/30/1993
• Est. Priority Date: 01/17/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Poradish, Frank J.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LE, HOANGANH T
• Application Number:
  US07/822,392
• Time in Patent Office: 438 Days
• Field of Search: 343/700 MS, 357/74, 357/80
• US Class Current: 343/700.0MS
• CPC Class Codes: H01Q 21/0087 Apparatus or processes specially adapted for manufacturing antenna arrays manufacturing waveguides H01P11/00
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them

Abstract

A phased array package using a cofired ceramic material system to integrate antenna elements and an hermetic multi-chip MMIC cavity into a single module to provide incorporation of microwave circuit geometries into a system which has been used in the prior art only for low frequency applications. The integration provides a package very similar to a conventional integrated circuit package with substantial cost reductions over the complicated microwave assemblies of the present art.

Claims

1. An integrated package which comprises:

(a) a plurality of high temperature co-fired stacked ceramic layers which have been co-fired at a temperature of from about 1500°

C. to about 1800°

C. in intimate relation with each other including top and bottom layers and at least one intermediate layer therebetween, each of said layers having a pair of opposing major surfaces;

(b) said at least one intermediate layer including a radiating antenna element disposed on a major surface thereof;

(c) at least one cavity in one of said top, bottom and at least one intermediate layer having a semiconductor chip therein;

(d) metallization disposed on a major surface of said at least one intermediate layer coupling said chip and said antenna element; and

(e) vias extending through the major surfaces of said at least one intermediate layer having electrically conductive material therein for interconnection with a layer intimate with said intermediate layer.

2. A package as set forth in claim 1 further including metallized grooves in the side walls of said layers.

3. A package as set forth in claim 2 wherein at least one of said top and bottom layers includes metallization on a major surface thereof.

4. A package as set forth in claim 3 further including an interconnect at an edge portion of said intermediate layer coupled to said metallization.

5. A package as set forth in claim 4 wherein said package is hermetic.

6. A package as set forth in claim 3 wherein said package is hermetic.

7. A package as set forth in claim 2 further including an interconnect at an edge portion of said intermediate layer coupled to said metallization.

8. A package as set forth in claim 7 wherein said package is hermetic.

9. A package as set forth in claim 2 wherein said package is hermetic.

10. A package as set forth in claim 1 wherein at least one of said top and bottom layers includes metallization on a major surface thereof.

11. A package as set forth in claim 10 further including an interconnect at an edge portion of said intermediate layer coupled to said metallization.

12. A package as set forth in claim 11 wherein said package is hermetic.

13. A package as set forth in claim 10 wherein said package is hermetic.

14. A package as set forth in claim 1 further including an interconnect at an edge portion of said intermediate layer coupled to said metallization.

15. A package as set forth in claim 14 wherein said package is hermetic.

16. A package as set forth in claim 1 wherein said package is hermetic.