Semiconductor memory circuit having switched voltage supply for data bus lines
First Claim
1. A semiconductor memory circuit comprising a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines, said pair of digit lines being connected through a switch circuit to a corresponding pair of data bus lines, which are in turn connected to a sense amplifier, the semiconductor memory circuit also including a voltage supply circuit composed of circuit elements having the same characteristics as that of circuit elements included in a circuit for determining a potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, said voltage supply circuit operating to generate, on the basis of the potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, a voltage to be applied to said pair of data bus lines when said pair of digit lines and said pair of data bus lines are not selected, the voltage generated by said voltage supply circuit being supplied to said pair of digit lines or said pair of data bus lines through another switch circuit which is turned on when said pair of digit lines and said pair of data bus lines are not selected.
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Accused Products
Abstract
A semiconductor memory circuit comprises a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines. The pair of digit lines are pulled up through a pair of load transistors, respectively, and connected through a pair of gate transistors to a corresponding pair of data bus lines, respectively, which are in turn connected to a sense amplifier and pulled down through a pair of driving transistors, respectively. A voltage supply circuit is provided which includes a voltage divider circuit composed of series-connected dummy transistors having the same characteristics as those of the load, gate and driving transistors which cooperate to determine a potential on the pair of data bus lines when the pair of digit lines and the pair of data bus lines are selected. On the basis of a reference voltage generated by the voltage divider circuit, the voltage supply circuit operates to generate a voltage to be supplied to the pair of data bus lines when the pair of digit lines and the pair of data bus lines are not selected. The voltage generated by the voltage supply circuit is supplied to the pair of digit lines or the pair of data bus lines through a switch circuit which is turned on when the pair of digit lines and the pair of data bus lines are not selected.
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Citations
6 Claims
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1. A semiconductor memory circuit comprising a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines, said pair of digit lines being connected through a switch circuit to a corresponding pair of data bus lines, which are in turn connected to a sense amplifier, the semiconductor memory circuit also including a voltage supply circuit composed of circuit elements having the same characteristics as that of circuit elements included in a circuit for determining a potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, said voltage supply circuit operating to generate, on the basis of the potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, a voltage to be applied to said pair of data bus lines when said pair of digit lines and said pair of data bus lines are not selected, the voltage generated by said voltage supply circuit being supplied to said pair of digit lines or said pair of data bus lines through another switch circuit which is turned on when said pair of digit lines and said pair of data bus lines are not selected.
- 2. A semiconductor memory circuit comprising a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines, said pair of digit lines being pulled up through a pair of load transistors, respectively, and connected through a pair of gate transistors to a corresponding pair of data bus lines, respectively, which are in turn connected to a sense amplifier and pulled down through a pair of driving transistors, respectively, the semiconductor memory circuit also including a voltage supply circuit which includes a voltage divider circuit composed of series-connected dummy transistors having the same characteristics as those of said load, gate and driving transistors which cooperate to determine a potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, said voltage supply circuit operating to generate, on the basis of a reference voltage generated by said voltage divider circuit, a voltage to be supplied to said pair of data bus lines when said pair of digit lines and said pair of data bus lines are not selected, the voltage generated by said voltage supply circuit is supplied to said pair of digit lines or said pair of data bus lines through a first switch circuit which is turned on when said pair of digit lines and said pair of data bus lines are not selected.
Specification