Programmable/reprogrammable structure combining both antifuse and fuse elements

• US 5,200,652 A
• Filed: 11/13/1991
• Issued: 04/06/1993
• Est. Priority Date: 11/13/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Roger R.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US07/791,797
• Time in Patent Office: 510 Days
• Field of Search: 307/202.1, 307/465, 307/465.1, 365/96, 365/102, 365/225.7
• US Class Current: 326/47
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence

Abstract

The present invention comprises a programmable structure for a integrated circuits, such as programmable read-only memory (PROM) or option selections/redundancy repair on dynamic random access memories (DRAMs), which utilizes both antifuse and fuse elements for multiple programming. Various combinations of anti-fuse and fuse elements (series or series-parallel combinations) will allow multiple programming of a given node in a particular circuit design to allow greater programming flexibility.

Claims

1. A programmable/reprogrammable structure in an integrated circuit comprising:

first and second conductors; and

a combination of one-time programmable elements coupled therebetween;

wherein said one-time programmable elements comprise an antifuse element coupled in series to a first fuse element via a third conductor thereby forming an antifuse/fuse series combination and a second fuse element coupled in parallel to said series combination, thereby providing a programming sequence having an initial state and first, second and third programmable states.

3. The programmable/reprogrammable structure of claim 1 wherein said programming sequence comprises a first shorted state, a first open state, a second shorted state and a second open state.

4. The programmable/reprogrammable structure of claim 1 wherein said first antifuse element is programmed as a short by applying a voltage potential between said first and third conductors.

5. The programmable/reprogrammable structure of claim 1 wherein said fuse element is programmed as an open by applying a voltage potential between said second and third conductors.

6. The programmable/reprogrammable structure of claim 1 wherein said second fuse element is programmed as an open by applying a voltage potential between said first and second conductors.

11. The programmable/reprogrammable structure of claim 1 wherein said integrated circuit comprises a memory device.

12. The integrated circuit of claim 11 wherein said memory device comprises a programmable read only memory.

13. The integrated circuit of claim 11 wherein said memory device comprises a random access memory.

14. The integrated circuit of claim 11 wherein said memory device comprises a programmable logic array.

15. The integrated circuit of claim 11 wherein said memory device comprises programmable array logic.

2. A programmable/reprogrammable structure in an integrated circuit comprising:

first and second conductors; and

a combination of one-time programmable elements coupled therebetween;

wherein said one-time programmable elements comprise a first antifuse element coupled in series to a first fuse element via a third conductor thereby forming an antifuse/fuse series combination and a second antifuse element coupled in parallel to said series combination, thereby providing a programming sequence having an initial state and first, second and third programmable states.

7. The programmable/reprogrammable structure of claim 2 wherein said programming sequence comprises a first open state, a first shorted state, a second open state and a second shorted state.

8. The programmable/reprogrammable structure of claim 2 wherein said first antifuse element is programmed as a short by applying a voltage potential between said first and third conductors.

9. The programmable/reprogrammable structure of claim 2 wherein said fuse element is programmed as an open by applying a voltage potential between said second and third conductors.

10. The programmable/reprogrammable structure of claim 2 wherein said second antifuse element is programmed as a short by applying a voltage potential between said first and second conductors.

16. The programmable/reprogrammable structure of claim 2 wherein said integrated circuit comprises a memory device.

17. The integrated circuit of claim 16 wherein said memory device comprises a programmable read only memory.

18. The integrated circuit of claim 16 wherein said memory device comprises a random access memory.

19. The integrated circuit of claim 16 wherein said memory device comprises a programmable logic array.

20. The integrated circuit of claim 16 wherein said memory device comprises programmable array logic.