Digital-to-analog converter with noise-free sigma-delta modulation

• US 5,200,750 A
• Filed: 11/21/1991
• Issued: 04/06/1993
• Est. Priority Date: 11/22/1990
• Status: Expired due to Term

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Fushiki, Tatsuo, Narusawa, Sadayuki
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US07/795,757
• Time in Patent Office: 502 Days
• Field of Search: 341/76, 341/77, 341/131, 341/143, 341/144
• US Class Current: 341/143
• CPC Class Codes: H03M 7/3011 of non-linear distortion, e.g. by temporarily adapting the operation upon detection of instability conditions avoiding instability by structural design H03M7/3035
• CPC Class Codes: H03M 7/3028 the quantiser being a single bit one
• CPC Class Codes: H03M 7/304 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Abstract

The digital-to-analog converter utilizes a modulator for effecting sigma-delta modulation of multi-bit input data to form a pattern of quantized output data so as to produce a pulse signal corresponding to the input data. The converter is provided with a zero detecting circuit for detecting a silent condition when the input data is continuously held at a zero level. An injecting circuit operates when the silent condition is detected for effecting continuous injection of a fractional reset signal into the modulator to gradually change an internal state of the modulator. A control circuit is provided to detect when the modulator reaches an optimum internal state effective to stabilize a varying idling pattern of the quantized output data for stopping the injection of the fractional reset signal so as to effect convergence of the varying idling pattern into a fixed idling pattern which is substantially free of an audible frequency component under the silent condition.

Claims

1. A digital-to-analog conversion apparatus comprising:

modulating means for effecting sigma-delta modulation of multi-bit input data to form a pattern of quantized output data so as to produce a pulse signal corresponding to the input data;

detecting means for detecting a silent condition when the input data is continuously held at a zero level;

injecting means operative when the silent condition is detected for effecting continuous injection of a fractional reset signal into the modulating means to gradually change an internal state of the modulating means; and

control means operative to detect when the modulating means reaches an optimum internal state effective to stabilize a varying idling pattern of the quantized output data for stopping the injection of the fractional reset signal so as to effect convergence of the varying idling pattern into a fixed idling pattern which is substantially free of an audible frequency component under the silent condition.

2. A digital-to-analog conversion apparatus according to claim 1;

wherein the control means includes means for monitoring an internal multi-bit data circulated in the modulating means to detect the optimum internal state when the monitored internal multi-bit data reaches an integer multiple value of the quantized output data during the course of the continuous injection of the fractional reset signal.

3. A digital-to-analog conversion apparatus according to claim 2;

wherein the injecting means includes means for injecting a fractional reset signal in the form of a carry signal effective to carry a lesser significant bit of an internal multi-bit data processed in the modulating means.

4. A digital-to-analog conversion apparatus according to claim 1;

including means for feeding to the modulating means a dither signal normally effective to suppress an audible noise in the pattern of the quantized output data, and wherein the control means includes means for suspending the feeding of the dither signal during the course of the injection of the fractional reset signal to achieve the optimum internal state in the modulating means.