Apparatus for binarizing images

• US 5,200,841 A
• Filed: 05/22/1991
• Issued: 04/06/1993
• Est. Priority Date: 05/25/1990
• Status: Expired due to Fees

• Current Assignee: Nikon Corporation
• Original Assignee: Nikon Corporation
• Inventors: Kotaki, Kenichi, Kimura, Hideo, Takemoto, Shigeru
• Primary Examiner(s): Coles, Sr., Edward L.
• Assistant Examiner(s): Grant, II, Jerome
• Application Number:
  US07/704,223
• Time in Patent Office: 685 Days
• Field of Search: 358/401, 358/429, 358/444, 358/445, 358/443, 358/447, 358/448, 358/452, 358/453, 358/454, 358/455, 358/456, 358/457, 358/458, 358/460, 358/461, 358/462, 358/463, 358/465 , 358/467
• US Class Current: 358/2.99
• CPC Class Codes: G06V 10/28 Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns
• CPC Class Codes: H04N 1/4055 producing a clustered dots or a size modulated halftone pattern

Abstract

The invention provides an image binarizing apparatus which includes multi-value image window circuitry for retrieving multi-value image data; a first binarizing circuit for binarizing the multi-value image data in accordance with a variable threshold determined based on the multi-value image data of pixels around a desired pixel; a second binarizing circuit for binarizing the multi-value image data in accordance with a predetermined threshold; and binary image window circuitry for retrieving image data which has been binarized by the second binarizing circuit. The image binarizing apparatus further includes edge detecting circuitry for comparing and collating binary two-dimensional image data obtained by the binary image window circuitry with edge templates each having a predetermined angle; memory circuitry for storing two types of smoothly binarized data in addresses which are generated based not only on the multi-value image data obtained by the multi-value image window circuitry, but also on the edge detection data which is output from the edge detecting circuitry; and selecting circuitry for selecting either one of the two types of smooth binary image data which are output either from the first binarizing circuit or from the memory circuitry.

Claims

1. 1 An image binarizing apparatus for binarizing the data item of a desired pixel among the multi-value image data items of pixels composed of plural bits, the multi-value image data items being output from an image taking device in a time series manner, said image binarizing apparatus comprising:

multi-value image window circuitry for obtaining said multi-value image data items in the form of two dimensions, whereby said multi-value image window circuitry cuts a two-dimensional image in a small field of vision from an image plane to be taken;

a first binarizing circuit for binarizing said multi-value image data items in accordance with a variable threshold which is determined based on said multi-value image data items of the pixels around said desired pixel;

a second binarizing circuit for binarizing said multi-value image data items in accordance with a predetermined threshold;

binary image window circuitry for obtaining image data which has been binarized by said second binarizing circuit, whereby said binary image window circuitry cuts a binary two-dimensional image in a small field of vision from an image plane to be taken;

edge detecting circuitry for comparing and collating the binary two-dimensional image data obtained by said binary image window circuitry with edge templates each having a predetermined angle, whereby said edge detecting circuitry detects whether or not the position of said desired pixel is on an edge, and outputs an edge direction in the form of edge detection data when the position of said desired pixel is on the edge;

memory circuitry for storing two types of smoothly binarized data in addresses which are generated based not only on the multi-value image data items obtained by said multi-value image window circuitry, but also on the edge detection data which is output from said edge detecting circuitry, the two types of smoothly binarized data stored in said memory circuitry being dependent on the smooth binary image data of a pixel adjacent to said desired pixel in said edge direction, said memory circuitry outputting two types of smooth binary image data in the addresses which correspond to said multi-value image data items and said edge detection data; and

selecting circuitry for selecting either one of the two types of smooth binary image data which are output either from said first binarizing circuit or from said memory circuitry, whereby when said edge detecting circuitry detects that an edge is not present, said selecting circuitry selects an output from said first binarizing circuit, while on the contrary, when said edge detecting circuitry detects that an edge is present, said selecting circuitry selects either one of the two types of smooth binary image data which are output from said memory circuitry, this selection being based on the smooth binary image data of the pixel adjacent to said desired pixel in the edge direction.

2. An image binarizing apparatus according to claim 1, wherein said second binarizing circuit binarizes said multi-value image data items by using a level at the center of said multi-value image data items as a threshold.

3. An image binarizing apparatus according to claim 1, said first binarizing circuit including:

a window circuit which arranges said multi-value image data items in a two-dimensional N×

N window, and which obtains both the image data of a desired pixel within said window and the image data of plural pixels around said desired pixel;

a mean value circuit for determining the mean value of the image data of the plural pixels around said desired pixel, which image data is obtained by said window circuit;

a threshold circuit for calculating a threshold based on the mean value determined by said mean value circuit; and

a comparator for binarizing the image data of said desired pixel in accordance with the threshold calculated by said threshold circuit.

4. An image binarizing apparatus according to claim 1, wherein said edge templates of said edge detecting circuitry are provided for angles of zero degree, 45 degrees, 90 degrees, and 135 degrees, and wherein said memory circuitry includes:

a first latch circuit for latching zero-degree edge multi-value data items which are arranged at an angle of zero degree and are among said multi-value image data items;

a second latch circuit for latching 45-degree edge multi-value data items which are arranged at an angle of 45 degrees and are among said multi-value image data items;

a third latch circuit for latching 90-degree edge multi-value data items which are arranged at an angle of 90 degrees and are among said multi-value image data items;

a fourth latch circuit for latching 135-degree edge multi-value data items which are arranged at an angle of 135 degrees and are among said multi-value image data items;

a data selecting circuit for selecting, based on an output from said edge detecting circuitry, the contents of said first, second, third, and fourth latch circuits; and

look-up table circuitry for inputting, in the form of an address signal, both data selected by said data selecting circuits and an output from an edge direction selecting circuit, said look-up table circuitry outputting adjacent white data P_W and adjacent black data P_B in the form of said two types of smooth binary image data.

5. An image binarizing apparatus according to claim 1, wherein said selecting circuitry includes image selecting circuitry and smooth binary window circuitry, wherein when said edge detecting circuitry detects that an edge is not present, said image selecting circuitry selects the output from said first binarizing circuit, while on the contrary, when said edge detecting circuitry detects that an edge is present, said image selecting circuitry selects either one of the two types of smooth binary image data which are output from said memory circuitry, this selection being based on the smooth binary image data of the pixel adjacent to said desired pixel in the edge direction, and wherein said smooth binary window circuitry forms a two-dimensional window composed of the smooth binary image data which is selected by said image selecting circuitry to which the smooth binary image data of the pixel adjacent to said desired pixel in said edge direction, is input.

6. An image signal binarizing apparatus for binarizing the data item of a desired pixel among multi-value image data items of pixels composed of plural bits, the multi-value image data items being output from an image taking device in a time series manner, said image signal binarizing apparatus comprising:

multi-value image window circuitry for obtaining said multi-value image data items in the form of two dimensions, whereby said multi-value image window circuitry cuts a two-dimensional image in a small field of vision from an image plane to be taken;

a binarizing circuit for binarizing said multi-value image data items in accordance with a predetermined threshold;

binary image window circuitry for obtaining image data which has been binarized by said binarizing circuit, whereby said binary image window circuitry cuts a binary two-dimensional image in a small field of vision from an image plane to be taken;

edge detecting circuitry for comparing and collating binary two-dimensional image data retrieved by said binary image window circuitry with edge templates each having a predetermined angle, whereby said edge detecting circuitry detects whether or not the position of said desired pixel is on an edge, and outputs an edge direction in the form of edge detection data when the position of said desired pixel is on the edge;

memory circuitry for storing two types of smoothly binarized data in addresses which are generated based not only on the multi-value image data items obtained by said multi-value image window circuitry, but also on the edge detection data which is output from said edge detecting circuitry, the two types of smoothly binarized data stored in said memory circuitry being dependent on the smooth binary image data of a pixel adjacent to said desired pixel in said edge direction, said memory circuitry outputting two types of smooth binary image data in the addresses which correspond to said multi-value image data items and said edge detection data; and

selecting circuitry for selecting either one of the two types of smooth binary image data which are output either from said binarizing circuit or from said memory circuitry, whereby when said edge detecting circuitry detects that an edge is not present, said selecting circuitry selects an output from said binarizing circuit, while on the contrary, when said edge detecting circuitry detects that an edge is present, said selecting circuitry selects either one of the two types of smooth binary image data which are output from said memory circuitry, this selection being based on the smooth binary image data of the pixel adjacent to said desired pixel in said edge direction.

7. An image signal binarizing apparatus for binarizing multi-value image data, comprising:

a window circuit for arranging multi-value image data having been input in a two-dimensional N×

N window to obtain both the image data of a predetermined pixel within said window and the image data of plural pixels around said predetermined pixel;

a mean value circuit for determining the mean value of the image data of the plural pixels around said predetermined pixel, which image data is obtained by said window circuit;

a threshold circuit for calculating a threshold based on the mean value determined by said mean value circuit; and

a comparator for binarizing the image data of said predetermined pixel in accordance with the threshold calculated by said threshold circuit.