Serial access semiconductor memory device and operating method therefor

• US 5,200,925 A
• Filed: 07/08/1991
• Issued: 04/06/1993
• Est. Priority Date: 07/29/1988
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Morooka, Yoshikazu
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): LANE, JOHN A
• Application Number:
  US07/728,323
• Time in Patent Office: 638 Days
• Field of Search: 365/73, 365/189.4, 365/189.5, 365/189.12, 365/219, 365/230.03, 365/230.04, 365/234, 365/240, 365/233, 365/230.05, 340/749, 340/800, 340/801, 340/802, 340/803
• US Class Current: 365/219
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence

Abstract

A serially accessible memory device includes a plurality of memory cell array blocks, a plurality of input buffers each separately provided for each cell array block for receiving different data in a data stream, a plurality of output buffers each separately provided for each memory cell array block, and a plurality of registers each separately provided for each memory cell array block for effectuating data transfer collectively to and from corresponding memory cell array blocks at the same time. All of the registers shift data received from corresponding input buffer to latch the data therein in response to a single clock signal in a data writing operation and also shift latched data received from corresponding array block to provide the data to corresponding output buffer in response to another single clock signal in data reading operation. Both the shifting clock signals are derived from an external clock defining the device operation rate.

Claims

1. A serial access semiconductor memory device, comprising:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different,

means for providing an external clock signal and a write/read enabling signal; and

logic means responsive to said external clock signal and said write/read enabling signal for generating an internal clock signal;

wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal, and the relationship of operation timing between said plurality of register means and said plurality of input buffer means during a data writing operation differs from the relationship of operation timing between said plurality of register means and said plurality of output buffer means during a data reading operation.

2. A device in accordance with claim 1, wherein said internal clock signal generating means include means for providing a write clock signal having a first activating timing for the data write operation and providing a read clock signal having a second activating timing, different from said first activating timing, for the data reading operation.

3. A device in accordance with claim 1, wherein said internal clock signal generating means include means for providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in the data reading operation.

4. A device in accordance with claim 1, wherein said internal clock generating means include means for providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in the data writing operation.

5. A serial access memory device, comprising:

a first memory cell array having a plurality of memory cells,

a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array;

a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal;

a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal;

a second memory cell array having a plurality of memory cells,

a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array;

a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal;

a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal;

means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; and

means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal;

wherein the relationship of operation timing between said registers and said input buffers differs from the relationship of operation timing between said registers said output buffers.

6. A method for accessing a serially accessible memory device, said memory device including:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means being capable of data latching and shifting data,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffers means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, said method including the steps of;

providing an external clock signal and a write/read enabling signal;

generating an internal clock signal in response to said external clock signal; and

applying said internal clock signal in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal, and the relationship of operation timing between said plurality of register means and said plurality of input buffer means during a data writing operation differs from the relationship of operation timing between said plurality of register means and said plurality of output buffer means during a data reading operation.

7. A method according to claim 6,

wherein said internal clock signal generating step includes providing clock signals different in activating timing for the data write operation and the data reading operation.

8. A method according to claim 6,

wherein said internal clock signal generating step includes providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in the data reading operation.

9. A method according to claim 6,

wherein said internal clock generating step includes providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in the data writing operation.

10. A video random access memory device (VRAM) for reading and writing pixel data, comprising:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different,

means for dividing down a chrominance subcarrier; and

means responsive to said divided down chrominance subcarrier and a write/read enabling signal for deriving an internal clock signal;

wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in responsive to the same internal clock signal, and the relationship of operation timing between said plurality of register means and said plurality of input buffer means during a data writing operation differs from the relationship of operation timing between said plurality of register means and said plurality of output buffer means during a data reading operation.

11. A VRAM in accordance with claim 10, wherein said internal clock signal deriving means include means for providing a write clock signal having a first activating timing for the data writing operation and providing a read clock signal having a second activating timing, different from said first activating timing, for the data reading operation.

12. A VRAM in accordance with claim 10, wherein said internal clock signal deriving means include means for providing a clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in the data reading operation.

13. A VRAM in accordance with claim 10, wherein said internal clock deriving means include means for providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in the data writing operation.

14. A video random access memory comprising:

a first memory cell array having a plurality of memory cells,

a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array;

a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal;

a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal;

a second memory cell array having a plurality of memory cells,

a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array;

a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal;

a second input buffer receiving the incoming data for providing selectively among the incoming data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal;

means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register;

means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal; and

means for generating said first and second clock signals by dividing means a chrominance subcarrier externally applied;

wherein the relationship of operation timing between said registers and said input buffers differs from the relationship of operation timing between said registers and said output buffers.

15. A method for serially accessing a video random access memory, said random access memory comprising:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means being capable of data latching and shifting data operations,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, said method including the steps of;

dividing down a chrominance subcarrier externally applied;

deriving an internal clock signal in response to said divided down chrominance subcarrier and a read/write enabling signal externally applied; and

applying said internal clock signal in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal, and the relationship of operation timing between said plurality of register means and said plurality of input buffer means during a data writing operation differs from the relationship of operation timing between said plurality of register means, and said plurality of output buffer means during a data reading operation;

16. A method in accordance with the claim 15, wherein said step of generating the internal clock signal includes the step of generating clock signals different in activating timing for the data writing operation and for the data reading operation.

17. A serial access semiconductor memory device, comprising:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output means for each of the memory cell array blocks is different,

means for providing an external clock signal and a write/read enabling signal; and

logic means responsive to said external clock signal and said write/read enabling signal for generating an internal clock signal, wherein said logic means include means for providing a write clock signal having a first activating timing for a data writing operation and providing a read clock signal having a second activating timing, different from said first activating timing, for a data reading operation;

wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

18. A serial access semiconductor memory device, comprising:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output means for each of the memory cell array blocks is different,

means for providing an external clock signal and a write/read enabling signal; and

logic means responsive to said external clock signal and said write/read enabling signal for generating an internal clock signal, wherein said logic means include

(i) means for providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in a data reading operation, and

(ii) means for providing a clock signal as said internal clock signal in syncrhonization with operation of one input buffer means among said plurality of input means in a data writing operation;

wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

19. A serial access memory device, comprising:

a first memory cell array having a plurality of memory cells,

a first shift registers for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array;

a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said fist register to an output node of said memory device, based on a first clock signal;

a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal;

a second memory cell array having a plurality of memory cells,

a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array;

a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal;

a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written to a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal;

means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; and

means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal,

whereby activating timing for the data reading operation provided by said first control signal is different from the activating timing for the data writing operation provided by said second control signal.

20. A serial access memory device, comprising:

a first memory cell array having a plurality of memory cells,

a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array;

a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal;

a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal;

a second memory cell array having a plurality of memory cells,

a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array;

a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal;

a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array of said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal;

means for generating a first control signal in phase with said first clock signal and thereby in synchronization with operation of said first output buffer in the data reading operation, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; and

means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal and in synchronization with operation of the second input buffer in the data writing operation.

21. A method for accessing a serially accessible memory device, said memory device including:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means being capable of data latching and shifting data,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential dat stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, said method including the steps of;

providing an external clock signal and a write/read enabling signal;

generating an internal clock signal in response to said external clock signal, said generating step including providing clock signals different in activating timing for a dat writing operation and a data reading operation; and

applying said internal clock signal in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

22. A method for accessing a serially accessible memory device, said memory device including:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending dat from and to among cells on a selected row in the corresponding block, each of said plurality of register means being capable of data latching and shifting data,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, said method including the steps of;

providing an external clock signal and a write/read enabling signal;

generating an internal clock signal in response to said external clock signal by

(i) providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in a data reading operation, and

(ii) providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in a data writing operation; and

applying said internal clock signal in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

23. A video random access memory device (VRAM) for reading and writing pixel data, comprising:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving an sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register mean for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different,

means for dividing down a chrominance subcarrier; and

means responsive to said divided down chrominance subcarrier and a write/read enabling signal for deriving an internal clock signal, wherein said internal clock signal deriving mean include means for providing a write clock signal having a first activating timing for a data writing operation and providing a read clock signal having a second activating timing, different from said first activating timing, for a data reading operation;

wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

24. A video random access memory device (VRAM) for reading and writing pixel data, comprising:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for dat latching and shifting data,

a plurality of input buffer means provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different,

means for dividing down a chrominance subcarrier; and

means responsive to said divided down chrominance subcarrier and a write/read enabling signal for deriving an internal clock signal, wherein said internal clock signal deriving means include

(i) means for providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in a data reading operation, and

(ii) means for providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in a data writing operation;

wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

25. A video random access memory comprising:

a first memory cell array having a plurality of memory cells,

a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array;

a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal;

a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal;

a second memory cell array having a plurality of memory cells,

a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array;

a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal;

a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal;

means for generating a first control signal in phase with said first clock signal and thereby in synchronization with operation of said first output buffer in the data reading operation, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register;

means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal; and

means for generating said first and second clock signals by dividing down a chrominance subcarrier externally applied,

whereby activating timing for the data reading operation provided by said first control signal is different from the activating timing for the data writing operation provided by said second control signal.

26. A video random access memory comprising:

a first memory cell array having a plurality of memory cells,

a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array;

a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal;

a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal;

a second memory cell array having a plurality of memory cells,

a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array;

a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock

a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal;

means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register;

means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal and in synchronization with operation of the second input buffer in the data writing operation; and

means for generating said first and second clock signals by dividing down a chrominance subcarrier externally applied.

27. A method for serially accessing a video random access memory, said random access memory comprising:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means being capable of data latching and shifting data operations,

a plurality of input holder means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register mean for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, said method including the steps of;

dividing down a chrominance subcarrier externally applied;

deriving an internal clock signal in response to said divided down chrominance subcarrier and a read/write enabling signal externally applied, said deriving step including providing clock signals different in activating timing of a data writing operation and the data reading operation; and

applying said internal clock signal in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

28. A method for serially accessing a video random access memory, said random access memory comprising:

a memory cell array divided into a plurality of blocks,

a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means being capable of data latching and shifting data operations,

a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream,

a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, said method including the steps of;

dividing down a chrominance subcarrier externally applied;

deriving an internal clock signal in response to said divided down chrominance subcarrier and a read/write enabling signal externally applied by

(i) providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in a data reading operation, and

(ii) providing a clock signal as said internal clock signal is synchronization with operation of one input buffer means among said plurality of input means in a data writing operation; and

applying said internal clock signal in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.