Device and method for defect handling in semi-conductor memory

• US 5,200,959 A
• Filed: 10/17/1989
• Issued: 04/06/1993
• Est. Priority Date: 10/17/1989
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Gross, Stephen, Norman, Robert D.
• Primary Examiner(s): Beausoliel, Robert W.
• Assistant Examiner(s): HUA, LY
• Application Number:
  US07/422,949
• Time in Patent Office: 1,267 Days
• Field of Search: 371/21.6, 371/10.1, 371/10.2, 371/11.1, 364/245.3, 364/285.3, 364/970.1
• US Class Current: 714/723
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

A solid-state memory array such as an electrically erasable programmable read only memory (EEprom) or Flash EEprom array is used to store sequential data in a prescribed order. The memory includes a first information list containing addresses and defect types of previously detected defects. The defects are listed in the same prescribed order as that of the data. Only a simple controller is required to reference the information list so that writing or reading of the data will skip over the defective locations in the memory. New defects may be detected during writing by failure in verification, and those new defects will also be skipped. The memory also includes a second information list maintained by the controller. As data is written to the memory, addresses of file-markers and defects detected by write failure are entered into the list in the same prescribed order. This second list is referenced with the first list by the controller in subsequent reading to skip over both the previously and the newly detected defects.

Claims

1. A method for handling defects of memory cells in a solid-state memory array comprising the steps of:

assigning an address to each memory cell according to a prescribed order;

detecting a first set of defects of the memory array and determining the address and type of each defect in the first set, said first set being detected prior to accessing of the memory;

storing in the memory array the first set of defects, each defect being labeled by the address and type thereof and arranged by address according to the prescribed order; and

skipping over the defects while accessing the memory array by referencing the ordered first list such that a number of memory cells appropriate to the defect type are skipped over.

2. A method for handling defects in memory cells in a solid-state memory array as in claim 1, wherein accessing the memory array includes writing data sequentially block by block thereto, verifying data in each write block after being written and before the writing of the next block, and the step of skipping over the defects while writing to the memory array further comprises:

storing in the memory array a second ordered list of file-markers, said file-markers providing demarcation addresses and identification of files written to the memory array;

detecting any defects in each write block by failure in verifying the data therein and skipping over any failed write block;

storing the addresses of any failed write block in the second ordered list such that the file-markers and the failed write blocks are ordered according to the prescribed order.

3. A method for handling defects in memory cells in a solid-state memory array as in claim 1, wherein accessing the memory array includes reading data sequentially block by block therefrom, and the step of skipping over the defects while reading from the memory array further comprises:

skipping over the defects by referencing both the first ordered list of the previously detected defects and the second ordered list of failed write blocks such that a number of memory cells appropriate to the defect type are skipped over.

4. A solid-state memory system for storing sequential data, comprising:

a memory array formed by a plurality of memory cells;

a data portion of the memory array usable for storing data files, said data portion having memory cells that are accessible in a prescribed order;

a first information list in the memory array, said first information list including an ordered directory of previously detected defects of the data portion, each defect being a cluster of one or more defective memory cells classifiable by defect type, and said ordered directory listing each defect'"'"'s location and type according to the prescribed order of the memory cells in the data portion;

a controller connected to the memory array for controlling access operations thereof, said controller accessing the memory cells in the data portion in the prescribed order while responsive sequentially to the first information list for skipping over a number of defective memory cells appropriate for its defect type at each defect'"'"'s location.

5. A solid-state memory system for storing sequential data as in claim 4, wherein:

each defect type includes that of column defect, row defect, erase-block defect, write-block defect and bit defect.

6. A solid-state memory system for storing sequential data as in claim 5, said first information list further including:

an ordered subdirectory of previously detected defects of the column defect type, said ordered subdirectory listing the column defects according to the prescribed order of the data portion;

wherein

the controller is also responsive sequentially to the ordered subdirectory of column defects when skipping over the previously detected defects.

7. A solid-state memory system for storing sequential data as in claim 6, wherein said memory array is an Electrically Erasable Programmable Read Only Memory (EEprom) or Flash EEprom.

8. A solid-state memory system for storing sequential data as in claim 6, wherein said memory array is detachably connected to the controller.

9. A solid-state memory system for storing sequential data as in claim 5, said first information list further comprising:

an ordered subdirectory of previously detected defects of the column defect type, said ordered subdirectory listing the column defects according to the prescribed order of the data portion;

a buffer in the controller for storing one or more items of the subdirectory; and

wherein

the controller is responsive sequentially to the ordered subdirectory of column defects in the buffer when skipping over the previously detected defects.

10. A solid-state memory system for storing sequential data as in claim 9, wherein said memory array is an Electrically Erasable Programmable Read Only Memory (EEprom) or Flash EEprom.

11. A solid-state memory system for storing sequential data as in claim 9, wherein said memory array is detachably connected to the controller.

12. A solid-state memory system for storing sequential data as in claim 5, wherein said memory array is an Electrically Erasable Programmable Read Only Memory (EEprom) or Flash EEprom.

13. A solid-state memory system for storing sequential data as in claim 5, wherein said memory array is detachably connected to the controller.

14. A solid-state memory system for storing sequential data as in claim 4, further comprising:

a second information list in the memory array maintained by the controller, said second list including an ordered directory of files stored in the data portion and defects detected while writing the files, said ordered directory of files and defects listing the files and defects according to the prescribed order of the data portion;

wherein

the controller accesses the memory cells in the data portion in the prescribed order thereof while responsive sequentially to the first list for skipping over the previously detected defects as well as to the second information list for skipping over defects detected while writing the files.

15. A solid-state memory system for storing sequential data as in claim 14, wherein:

the plurality of memory cells are assigned addresses in a prescribed order with a first end and second end;

the first information list occupies the memory cells from the first end and extends therefrom;

the data portion is substantially adjacent the first information list and extendable therefrom; and

the second list occupies the memory cells from the second end and is extendable therefrom.

16. A solid-state memory system for storing sequential data as in claim 15, wherein said memory array is an Electrically Erasable Programmable Read Only Memory (EEprom) or Flash EEprom.

17. A solid-state memory system for storing sequential data as in claim 15, wherein said memory array is detachably connected to the controller.

18. A solid-state memory system for storing sequential data as in claim 14, wherein:

the plurality of memory cells are assigned addresses in a prescribed order with a first end and second end;

the data portion occupies the first end and is extendable therefrom;

the first information list occupies the second end and extends therefrom; and

the second information list is substantially adjacent the first information list and is extendable therefrom.

19. A solid-state system for storing sequential data as in claim 18, wherein said memory array is an Electrically Erasable Programmable Read Only Memory (EEprom) or Flash EEprom.

20. A solid-state memory system for storing sequential data as in claim 18, wherein said memory array is detachably connected to the controller.

21. A solid-state memory system for storing sequential data as in claim 14, said controller further comprising:

a control means;

pointer means controlled by the control means for indicating the current accessing positions on the data portion, the first information list, the subdirectory of column defects and the second information list;

storage means controlled by the control means for holding the addresses of the current defects in the memory array;

comparator means for determining whether the current address in the data portion coincides with any one of the current defects, said control means being responsive to the comparator means; and

data manipulation means controlled by said control means for staging data such that data accessing of the data portion skips over defects.

22. A solid-state memory system for storing sequential data as in claim 21, wherein said memory array is an Electrically Erasable Programmable Read Only Memory (EEprom) or Flash EEprom.

23. A solid-state memory system for storing sequential data as in claim 21, wherein said memory array is detachably connected to the controller.

24. A solid-state memory system for storing sequential data as in claim 14, wherein said memory array is an Electrically Erasable Programmable Read Only Memory (EEprom) or Flash EEprom.

25. A solid-state memory system for storing sequential data as in claim 14, wherein said memory array is detachably connected to the controller.

26. A solid-state memory system for storing sequential data as in claim 4, wherein said memory array is an Electrically Erasable Programmable Read Only Memory (EEprom) or Flash EEprom.

27. A solid-state memory system for storing sequential data as in claim 4, wherein said memory array is detachably connected to the controller.