In-line piece-wise linear desynchronizer

• US 5,200,982 A
• Filed: 10/02/1991
• Issued: 04/06/1993
• Est. Priority Date: 10/02/1991
• Status: Expired due to Term

• Current Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Original Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Inventors: Weeber, William B.
• Primary Examiner(s): Chin, Stephen
• Application Number:
  US07/771,037
• Time in Patent Office: 552 Days
• Field of Search: 375/118, 375/119, 375/120, 370/102, 370/105.3, 370/108
• US Class Current: 375/372
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Abstract

An in-line piece-wise linear desynchronizer eliminates the need for very low bandwidth analog, phase lock loops to smooth phase jumps caused by pointer changes such as those associated with a DS-1 signal mapped into a SONET VT 1.5 payload. The desynchronizer comprises a digital elastic store position detection circuit, a digital frame induced jitter filter, a digital leak rate filter, and a digital frequency synthesizer (VCO). The magnitude of the jitter can be reduced to any level by adjusting the digital VCO resolution and digital leak rate filter time constant. The desynchronizer produces a digitally synthesized output clock which can then be coupled to an analog/digital phase lock loop for smoothing high frequency jitter in the synthesized output clock, thereby providing an in-line interface function.

Claims

1. A digital desynchronizer for smoothing phase jumps caused by pointer changes of a first signal operating in a first format mapped into a signal operating in a second format comprising:

A) digital elastic store means for generating a digital elastic store position detection output signal (FJTR), said means having means for receiving the write address and read address associated with the signal operating in the first format, as well as an input for receipt of a threshold signal which in turn is a function in part of the digital elastic store position detection output signal;

B) digital frame jitter filter means for generating a digital frame induced jitter filter output signal (DELTA) having an input connected to the elastic store position output signal (FJTR), said DELTA output signal being linear and proportional to the elastic store position output signal, said digital frame induced jitter filtering means also having means for generating said threshold signal, wherein said threshold signal is a function of the elastic store output signal (FJTR);

C) digital leak filter means connected to the DELTA output, for generating a digital leak rate filter output signal (VCO), said VCO signal being proportional to the desired transmission frequency of the signal in said first format;

D) digital VCO means connected to the VCO signal, for generating a clock signal operating at a frequency of the second format; and

E) means, connected to the clock signal, for generating said read address associated with the signal operating in the first format.

2. A digital desynchronizer as defined in claim 1, wherein the digital elastic store position detection means comprises first binary adder for subtracting the read adss count from the write address count and a second binary adder for subtracting the threshold signal from the output of the first adder and further comprising a decoder having an input connected to the output of the second adder for generating the FJTR output signal based upon the magnitude of the output of the second adder.

3. A digital desynchronizer as defined in claim 2, wherein the frame jitter filter means comprises a binary counter for counting the FJTR output signal, and an up/down counter connected to the output of the binary counter, said up/down counter having an output of which a portion thereof represents the value of the threshold signal, and an add one module connected to the output of the up/down counter for generating the value of DELTA.

4. A digital desynchronizer as defined in claim 3, wherein the leak filter means comprises an offset module, having an input connected to the DELTA output of the frame jitter means, said offset module having means for generating a non-continuous transfer function output for fault recovery purposes.

5. A digital desynchronizer as defined in claim 4, wherein the leak filter means in an in-line configuration of the desynchronizer further comprises a nominal module having an input connected to the DELTA output of the frame jitter means, wherein the nominal module comprises a binary counter for integrating the DELTA output of the frame jitter module.

6. A digital desynchronizer as defined in claim 5, wherein the leak filter means further comprises a first summer having on input connected to the DELTA output of the frame jitter means and a second input connected to the output of the offset module, the leak filter means further comprising a second summer having one input connected to the output of the first summer and a second input connected to the output of the nominal module so as to generate the VCO signal.

7. A digital desynchronizer as defined in claim 6, wherein the digital VCO means has a non-linear transfer function and has an input connected to a bias signal and means connected to said bias signal for adjusting the gain characteristics of the non-linear digital VCO based upon the value of the bias signal and thus adjusting the bandwidth of the desynchronizer.