Multiple address-space data processor with addressable register and context switching

• US 5,201,039 A
• Filed: 08/20/1990
• Issued: 04/06/1993
• Est. Priority Date: 09/30/1987
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Sakamura, Ken
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Harrity, Paul
• Application Number:
  US07/569,758
• Time in Patent Office: 960 Days
• Field of Search: 395/425, 395/400, 395/375, 395/650
• US Class Current: 711/201
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/3555 using scaling, e.g. multiplication of index
• CPC Class Codes: G06F 9/462 with multiple register sets
• CPC Class Codes: G06F 9/463 Program control block organisation

Abstract

Two or more address spaces are provided in a data processor. One of the address spaces comprises control registers so that the control registers can be accessed using instructions having an address in the second address space. High-speed context switching can be accomplished by allotting the context-saving area to the second address space. The context can be saved in various formats specified by a context format register.

Claims

1. In a data processor for processing data according to a program which includes a plurality of executable instructions, the data processor having a plurality of registers, apparatus for storing information comprising:

a first portion of byte-addressable memory for storing data and programs, at least some of the byte-addresses for said first portion of byte-addressable memory forming a first address space in which programs and data are mapped, each address in said first address space is either an operand address or an instruction address of at least one of said plurality of instructions; and

a second portion of byte-addressable memory, at least some of the byte-addresses for said second portion forming a second address space different from said first address space, at least some addresses of said second address space being addresses which also occur in said first address space, wherein at least a first of said registers has a byte address, said first register being mapped by said byte address to said second address space such that said first register is accessible using a second instruction which has an operand address in said second address space, said byte address of said first register in said second address space being identical to said operand address or instruction address of said one of said instructions in said first address space

whereby said data processor accesses said operand address or said instruction address in said first address space by executing said one of said instructions having said operand address or said instruction address in said first address space; and

whereby said data processor accesses said first register in said second address space by executing said second instruction having said operand address in said second address space.

2. The apparatus as set forth in claim 1, wherein:

at least one of said plurality of instructions is an instruction to save a context of said data processor into said second address space; and

at least one of said plurality of instructions is an instruction to restore a context from said second address space.

3. The apparatus as claimed in claim 2, wherein said context includes the contents of at least a first of said registers.

4. The apparatus as set forth in claim 1, wherein said first register is mapped to a first address in said second address space and wherein said first register comprises a plurality of independent fields, at least one of said independent fields of said first register being mapped to a second address in said second address space different from said first address of said first register.

5. The apparatus as claimed in claim 1, wherein all of said plurality of registers are mapped to said second address space.

6. Apparatus, as claimed in claim 1, wherein substantially all addresses in said second space occur in said first address space.

7. In a data processing system for processing data according to a program which includes a plurality of executable instructions, the data processing system having a main processor and a co-processor, said main processor having at least a first associated register and said co-processor having at least a second associated register, apparatus for storing information, comprising:

a first portion of byte-addressable memory for storing data and programs, at least some of the byte addresses for said first portion of byte-addressable memory forming a first address space, each address in said first address space is either an operand address or an instruction address of at least one of said plurality of instructions; and

a second portion of byte-addressable memory, at least some of the byte addresses for said second portion of byte-addressable memory forming a second address space, different from said first address space, at least some addresses of said second address space being addresses which also occur in said first address space, at least said first register associated with said main processor having a first byte address and said second register associated with said co-processor having a second byte address, said first and second registers being mapped to said second address space by said first and second byte addresses, said first and second registers being accessible using a respective second of said plurality of instructions which has an operand address in said second address space, at least one of said first and second byte addresses of said first and second registers in said second address space being identical to said operand address or instruction address of a respective one of said plurality of instructions in said first address space

whereby said main processor and said co-processor access a respective said operand address or said instruction address in said first address space by executing said respective one of said plurality of instructions having said operand address or said instruction address in said first address space; and

whereby said main processor and said co-processor access said first and second registers in said second address space by executing said respective second of said plurality of instructions having said operand address in said second address space.

8. In a data processor for processing data according to a program which includes a plurality of executable instructions, apparatus for storing information comprising:

a first portion of byte-addressable memory for storing data and programs, at least some of the byte-addresses for said first portion of byte-addressable memory forming a first address space in which programs and data are mapped, each address in said first address space is either an operand address or an instruction address of at least a first of said plurality of instructions;

a second portion of byte-addressable memory, at least some of the byte-addresses for said second portion forming a second address space different from said first address space, at least some addresses of said second address space being addresses which also occur in said first address space;

the data processor executing at least a first of said plurality of instructions to save a context of said data processor into said second address space;

the data processor executing at least a second of said plurality of instructions, different from said first instruction, to restore said context from said second address space;

the data processor executing at least a third of said plurality of instructions, different from said first instruction, to save a context of said data processor into said first address space; and

the data processor executing at least a fourth of said plurality of instructions, different from said second instruction, to restore said context from said first address space.

9. The apparatus as set forth in claim 8, further comprising:

register means for specifying a format for storage of said context.

10. The apparatus as claimed in claim 8, further comprising:

means for specifying a format from among at least three formats for storage of a context block;

wherein said first instruction is an instruction to save a context according to the format specified in said means for specifying a format; and

wherein said second instruction is an instruction to restore a context according to the format specified in said means for specifying a format.

11. In a data processor for processing data according to a program which includes a plurality of executable instructions, including instructions for saving and restoring a context, apparatus for storing information comprising:

a first portion of byte-addressable memory for storing data and programs, at least some of the byte-addresses for said first portion of byte-addressable memory forming a first address space in which programs and data are mapped, each address in said first address is space is either an operand address or an instruction address of at least a first of said plurality of instructions;

a second portion of byte-addressable memory, at least some of the byte addresses for said second portion forming a second address space different from said first address space, at least some addresses of said second address space being addresses which also occur in said first address space, said second address space being accessible using said instructions for saving and restoring a context;

means for specifying into which address space a context block is to be stored according to one of said plurality of instructions;

the data processor executing at least a first of said plurality of instructions to save the context of a process into said address space specified by said means for specifying; and

the data processor executing at least a second of said plurality of instructions, different from said first instruction, to restore said context from the address space specified by said means for specifying.

12. In a data processor for processing data according to a program which includes a plurality of executable instructions, the data processor having a plurality of registers, a method for storing information comprising:

providing a first portion of byte-addressable memory for storing data and instructions, at least some of the byte-addresses for said first portion of byte-addressable memory forming a first address space in which data and instructions are mapped;

accessing at least a first address in said first address space by executing at least one of said instructions having an operand address in said first address space;

providing a second portion of byte-addressable memory, at least some of the byte-addresses for said second portion forming a second address space different from said first address space wherein at least a first of said registers is mapped by a byte address to said second address, at least some addresses of said second address space being addresses which also occur in said first address space; and

accessing said first register by executing a second of said instructions having an operand address in said second address space, said address of said first register in said second address space being identical to a data address or instruction address of said at least one instruction in said first address space.

13. The method as set forth in claim 12, further comprising:

executing an instruction to save a context in said data processor into said second address space; and

executing an instruction to restore a context from said second address space.

14. In a data processing system for processing data according to a program, which includes a plurality of executable instructions, the data processing system having a main processor and a co-processor, said main processor having at least a first associated register and said co-processor having at least a second associated register, a method for storing information, comprising:

providing a first portion of byte-addressable memory for storing data and programs, said byte-addressable memory having a plurality of storage locations addressable by a plurality of byte addresses at least some of the byte addresses for said first portion of byte-addressable memory forming a first address space;

executing at least one of said instructions, stored at an instruction address and having an operand address in said first address space;

providing a second portion of byte-addressable memory, at least some of the byte addresses for said second portion of byte-addressable memory forming a second address space, different from said first address space, at least some addresses of said second address space being addresses which occur in said first address space, at least said first register associated with said main processor having a first byte address and said second register associated with said co-processor having a second byte address, said first and second registers being mapped to said second address space by said first and second byte addresses;

accessing at least one of said first and second registers by executing a second of said plurality of instructions having an operand address in said second address space, the byte address of said one register in said second address space being identical to said operand address or instruction address of said one of said instructions in said first address space.

15. In a data processor for processing data according to a program which includes a plurality of executable instructions, including instructions for saving and restoring a context, a method for storing information comprising:

providing a first portion of byte-addressable memory for storing data and programs, at least some of the byte-addresses for said first portion of byte-addressable memory forming a first address space in which data and programs are mapped, each address in said first address space is either being usable as an operand address or an instruction address of at least a first of said plurality of instructions;

providing a second portion of byte-addressable memory, at least some of the byte-addresses for said second portion forming a second address space different from said first address space, said second address space being accessible using said instructions for saving and restoring a context, at least some addresses of said second address space being addresses which also occur in said first address space;

specifying, in a first of said plurality of instructions, into which address space a context block is to be stored;

saving the context of a process into said specified address space in response to said first instruction; and

restoring said context from the specified address space in response to a second instruction, different from said first instruction.

16. The method as claimed in claim 15, further comprising:

specifying a format from among at least three formats for storage of a context block;

wherein said step of saving includes saving a context according to said specified format; and

wherein said step of restoring includes restoring a context according to said specified format.