Asymmetrical non-volatile memory cell, arrays and methods for fabricating same

• US 5,202,576 A
• Filed: 06/25/1991
• Issued: 04/13/1993
• Est. Priority Date: 08/29/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wong, Man, Liu, David K.
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US07/723,700
• Time in Patent Office: 658 Days
• Field of Search: 357/23.5, 357/23.3, 365/185
• US Class Current: 257/315
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).

Claims

1. A non-volatile memory cell formed in a face of a layer of a semiconductor of a first conductivity type, comprising:

first and second heavily doped regions formed in said layer of semiconductor to be of a second conductivity type opposite said first conductive type, said first and second highly doped regions spaced by a channel region;

a first lightly doped region formed in said layer of a semiconductor to be of said second conductivity type, said lightly doped region formed adjacent said second heavily doped region;

a second lightly doped region formed adjacent said first heavily doped region wherein the dopant concentration of said second lightly doped region is substantially lower than the dopant concentration of said first lightly doped region;

a floating gate conductor insulatively overlying said channel area and insulatively overlying said first lightly doped region but not overlying said second lightly doped region; and

a control gate conductor capacitively coupled with said floating gate conductor.

2. The memory cell of claim 1, wherein said lightly doped regions are formed in said channel are.

3. The memory cell of claim 1, wherein said first heavily doped region comprises a source region and said second heavily doped region comprises a drain region.

4. The memory cell of claim 1, wherein:

said semiconductor layer comprises p-type material;

said heavily doped regions comprise n-type material; and

said lightly doped region comprises n-type material.

5. A non-volatile memory cell formed in a face of a layer of semiconductor of a first conductivity type, comprising:

a source region formed in said face to be of a second conductivity type opposite said first conductivity type;

a drain region formed in said face to be of said second conductivity type and spaced from said source region by a channel area;

a first lightly doped diffused region formed in said channel area adjacent said source region to be of said second conductivity type;

a second lightly diffused region formed in said channel area adjacent said drain region to be of said second conductivity type wherein the dopant concentration of said first lightly doped diffused region is less than the dopant concentration of said second lightly doped diffused region;

a floating gate conductor insulatively overlying said channel area and insulatively overlying said second lightly diffused region but not overlying said first lightly doped diffused region; and

a control gate conductor insulatively adjacent said floating gate.

6. The memory cell of claim 5, wherein:

said source region and said drain region comprise n+ material;

said first and second lightly doped diffused regions comprises n- material; and

said semiconductor layer comprises p- material.

7. A field effect transistor non-volatile memory cell formed in a layer of p-type semiconductor comprising:

a source including a heavily doped portion of n-type material and a lightly doped portion of n-type material, said lightly doped portion adjacent a channel are of said cell;

a drain spaced from said source by said channel area, said drain including a heavily doped portion of n-type material and a lightly doped potion of n-type material, said lightly doped portion adjacent said channel area, wherein the dopant concentration of said source lightly doped portion is substantially lower than the dopant concentration of said drain lightly doped portion;

a floating gate conductor insulatively overlying said channel area and insulatively overlying said lightly-doped portion of said drain but not overlying said lightly doped portion of said source; and

a control gate conductor insulatively adjacent said floating gate.

8. An array of asymmetrical, non-volatile memory cells formed in columns and in rows at an angle to the columns, at a face of a layer of semiconductor of a first conductivity type, comprising:

a plurality of elongated heavily doped regions spaced by a plurality of elongated channel areas, a pair of said doped regions and a respective said channel area forming a column of cells;

first and second lightly doped regions on opposite sides of each channel area and adjacent respective ones of said heavily doped regions, wherein the dopant concentration of said second lightly doped regions is less than the dopant concentration of said first lightly doped regions;

for each cell, a floating gate insulatively adjacent a respective portion of said channel and insulatively overlying said first lightly doped region, but not overlying said second lightly doped region; and

for each row, an elongated control gate conductor, insulatively adjacent said floating gates in said row.

9. The array of claim 8, wherein said heavily doped diffused regions comprise n+ material and said lightly doped diffused regions comprise n- material.

10. The array of claim 8, wherein a terminal of said floating gates is formed insulatively adjacent said selected lightly doped diffused regions.