Module-type semiconductor device of high power capacity

• US 5,202,578 A
• Filed: 09/16/1991
• Issued: 04/13/1993
• Est. Priority Date: 09/11/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hideshima, Makoto
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US07/760,281
• Time in Patent Office: 575 Days
• Field of Search: 357/68, 357/72, 357/75, 357/80, 357/38, 357/40, 357/41, 357/42, 357/43, 357/52, 357/59, 357/81, 361/392, 361/393, 361/395, 307/54, 307/270, 307/570, 307/572, 307/575
• US Class Current: 257/685
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 25/11 the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

One of a pair of the module type semiconductor devices, signal input terminals are located on the other side of current output terminals with respect to current input terminals, and that, in the other of a pair of the module type semiconductor devices, signal input terminals are mounted on the other side of current input terminals with respect to current output terminals. Distance of connections between element in the case of bridge connections may be shortened to the minimum. Since the signal input terminals may be located outside the bus bars, openings need not be made in the bus bar. Space or the bus bar'"'"'s surface area may be effectively used, with the result that a decrease in commutating inductance is achieved.

Claims

1. A subassembly for a semiconductor device of a high power capacity comprising:

a fist casing having terminals extending from a top surface including

a signal input terminal,

a current output terminal,

a current input terminal between the signal input terminal and the current output terminal, and

a power semiconductor device having a control input coupled to the signal input terminal, and a current path coupled between the current input terminal and the current output terminal;

a second casing, of substantially equivalent type of the first casing, having terminals extending from a top surface including

a signal input terminal,

a current input terminal, opposed to the current output terminal of the first casing,

a current output terminal between the signal input terminal and the current input terminal, and

a power semiconductor device having a control input coupled to the signal input terminal, and a current path coupled between the current input terminal and the current output terminal; and

means for electrically interconnecting the current output terminal of said first casing with the current input terminal of said second casing,

wherein said first and second casings are on a plane in a pair such that the current output terminal of said first casing and current input terminal of said second casing are in proximity, and opposed to each other

2. The subassembly for a semiconductor device according to claim 1, wherein said first and second casings are composed respectively of a resin.

3. The subassembly for a semiconductor device according to claim 1, wherein said power semiconductor devices include pairs of semiconductor chips having substantially equivalent electrical properties.

4. The subassembly for a semiconductor device according to claim 3, wherein said semiconductor chips have a layout common to said first and second casings.

5. The subassembly for a semiconductor device according to claim 1, wherein said terminals are screw terminals.

6. The subassembly for a semiconductor device according to claim 1, wherein said signal input terminals are fastening configuration terminals.

7. The subassembly for a semiconductor device according to claim 1, further comprising:

a first bus bar electrically interconnecting said opposing current input terminal and current output terminal and which extends upward as an electrode;

a second bus bar located parallel to and in proximity to one side of said first bus bar and electrically connected to the current output terminal of first casing; and

a third bus bar located parallel to and in proximity to the other side of said first bus bar and electrically connected to the current input terminal of said second casing.

13. The semiconductor device according to claim 7, wherein the bus bars are sufficiently close so as to mutually cancel magnetic fluxes generated therein.

16. The semiconductor device according to claim 7, wherein the first bus bar is at a spacing relative to the first and second casings.

8. A subassembly for a semiconductor device of a high power capacity comprising:

a first casing having a central top portion at a first level, a first portion on a side of the top portion at a level lower than the first level, and a second portion on an opposite side of the top portion at a level lower than the first level;

a pair of semiconductor chips sealed within the casing;

a first current input terminal and a first current output terminal extending out of the top portion of the first casing;

a first plurality of signal input terminals extending out of the first portion;

a second plurality of signal input terminals extending out of the second portion, each signal input terminal of the second plurality connected within the casing to a corresponding signal input terminal of the first plurality;

a second casing having a central top portion at a first level, a first portion on a side of the top portion at a level lower than the first level, and a second portion on an opposite side of the top portion at a level lower than the first level;

a pair of semiconductor chips sealed within the casing;

a second current input terminal and a second current output terminal extending out of the top portion of the second casing;

a first plurality of signal input terminals extending out of the first portion;

a second plurality of signal input terminals extending out of the second portion, each signal input terminal of the second plurality connected within the casing to a corresponding signal input terminal of the first plurality; and

means for electrically interconnecting the current output terminal of said first casing with the current input terminal of said second casing,

wherein said first and second casings are on a plane in a pair such that the current output terminal of said first casing and current input terminal of said second casing are in a vicinity and opposed to each other, and the first portion of the first casing is opposed to the second portion of the second casing.

9. The subassembly for a semiconductor device according to claim 8, wherein said casing is composed of a resin.

10. The subassembly for a semiconductor device according to claim 8, wherein said semiconductor chips have substantially equivalent electrical properties.

11. The subassembly for a semiconductor device according to claim 8, wherein the current input terminal, the current output terminal and the first and second pluralities of signal input terminals are, respectively, screw terminals.

12. The subassembly for a semiconductor device according to claim 8, wherein the current input terminal, the current output terminal and the first and second pluralities of signal input terminals are, respectively, fastening configuration terminals.

14. A subassembly for a semiconductor device of a high power capacity, comprising:

a first bus bar;

a second bus bar;

a third bus bar;

a first casing defining a central top portion at a first level, a first portion on a side of the top portion at a level lower than the first level, a second portion on an opposite side of the top portion at a level lower than the first level, and an interior portion, including

a semiconductor chip in the interior portion,

a current input terminal extending out of the top portion and electrically connected to the first bus bar,

a current output terminal extending out of the top portion,

a first plurality of signal input terminals extending out of the first portion, and

a second plurality of signal input terminals extending out of the second portion, each signal input terminal of the second plurality connected to a corresponding signal input terminal of the first plurality; and

a second casing, on a plane with the first casing, defining a central top portion at a first level, a first portion on a side of the top portion at a level lower than the first level, a second portion on an opposite side of the top portion at a level lower than the first level, and an interior portion, including

a semiconductor chip in the interior portion,

a current input terminal extending out of the top portion, opposed to the current output terminal of the first casing, and electrically coupled to the current output terminal of the first casing by the second bus bar, the second bus bar extending upward as an electrode, the first bus bar parallel to a side of the second bus bar, and

a current output terminal extending out of the top portion and electrically connected to the third bus bar, the third bus bar parallel to an opposite side of the second bus bar,

a first plurality of signal input terminals extending out of the first portion, and

a second plurality of signal input terminals extending out of the second portion, each signal input terminal of the second plurality connected to a corresponding signal input terminal of the first plurality,

wherein the first portion of the first casing is opposed to the second portion of the second casing.

15. The semiconductor device according to claim 14, wherein the bus bars are sufficiently close so as to mutually cancel magnetic fluxes generated therein.

17. The semiconductor device according to claim 14, wherein the second bus bar is at a spacing relative to the first and second casings.

18. A subassembly for a semiconductor device of a high power capacity comprising:

a first casing including

a signal input terminal extending from a first portion at a first level,

a current output terminal extending from a second portion at a level higher than the first level,

a current input terminal, between the signal input terminal and the current output terminal, extending from the second portion, and

a power semiconductor device having a control input coupled to the signal input terminal, and a current path coupled between the current input terminal and the current output terminal;

a second casing, of substantially equivalent type of the first casing, having terminals extending from a top surface including

a signal input terminal extending from a first portion at a first level,

a current input terminal, opposed to the current output terminal of the first casing, and extending from a second level higher than the first level,

a current output terminal, between the signal input terminal and the current input terminal, extending from the second level, and

a power semiconductor device having a control input coupled to the signal input terminal, and a current path coupled between the current input terminal and the current output terminal;

a bus bar connected between the current output terminal of the first casing and the current input terminal of the second casing;

means for electrically interconnecting the current output terminal of said first casing with the current input terminal of said second casing, wherein said first and second casings are on a plane in a pair such that the current output terminal of said first casing and current input terminal of said second casing are in a vicinity and opposed to each other, and the first portion of the first casing is opposed to the second portion of the second casing.

19. A subassembly used for a semiconductor device for providing a bridge connection, comprising:

a first casing having terminals extending from a top surface including

a signal input terminal;

a current output terminal;

a current input terminal between the signal input terminal and the current output terminal, and

a power semiconductor device having a control input coupled to the signal input terminal, and a current path coupled between the current input terminal and the current output terminal;

a second casing having terminals extending from a top surface including

a signal input terminal,

a current output terminal, facing the current input terminal of the first casing in a first direction,

a current input terminal between the signal input terminal and the current output terminal, and

a power semiconductor device having a control input coupled to the signal input terminal, and a current path coupled between the current input terminal and the current output terminal;

a third casing having terminals extending from a top surface including

a signal input terminal,

a current input terminal, facing the current input terminal of the first casing in a second direction perpendicular to the first direction,

a current output terminal between the signal input terminal and the current input terminal, and

a power semiconductor device having a control input coupled to the signal input terminal, and a current path coupled between the current input terminal and the current output terminal;

a fourth casing having terminals extending from a top surface including

a signal input terminal,

a current output terminal, facing the current input terminal of the third casing in the first direction, facing the current output terminal of the second casing in the second direction,

a current output terminal, between the signal input terminal and the current input terminal, and opposed to the current output terminal of the second casing, and

a power semiconductor device having a control input coupled to the signal input terminal, and a current path coupled between the current input terminal and the current output terminal;

a first bus bar connected to the current output terminals of the first and third casings;

a second bus bar connected to the current input terminals of the first and third casings, and to the current output terminals of the second and fourth casings; and

a third bus bar connected to the current input terminals of the second and fourth casings.

20. The subassembly for a semiconductor device according to claim 19, wherein the first, second, and third bus bars are each laterally removed from the signal input terminals of the first, second, third, and fourth casings.

26. The semiconductor device according to claim 19, wherein said bus bars have a wide surface area to decrease commutating inductance of a bridge connection, and are integrated with one another.

21. A subassembly used for a semiconductor device for providing a bridge connection, comprising:

a first, second, third and fourth casings, each casing defining a central top portion at a first level, a first portion on a side of the top portion at a level lower than the first level, a second portion on a opposite side of the top portion at a level lower than the first level, and an interior portion, each casing including

a current input terminal extending out of the top portion,

a current output terminal extending out of the top portion,

a first signal input terminal extending out of the first portion,

a second signal input terminal extending out of the second portion, and connected to the first signal input terminal, and

a semiconductor chip including a power semiconductor device having a control input coupled to the first and second signal input terminals, and a current path coupled between the current input terminal and the current output terminal, wherein

the current output terminal of the second casing faces the current input terminal of the first casing in a first direction,

the current input terminal of the third casing faces the current input terminal of the first casing is a second direction perpendicular to the first direction, the current output terminal of the third casing faces the current output terminal of the first casing is the second direction,

the current input terminal of the fourth casing faces the current output terminal of the third casing in the first direction, and the current input of the fourth casing faces the current input terminal of the second casing in the second direction, and

wherein the device further includes

a first bus bar connected to the current output terminals of the first and third casings;

a second bus bar connected to the current input terminals of the first and third casings, and to the current output terminals of the second and fourth casings;

a third bus bar connected to the current input terminals of the second and fourth casings.

22. The subassembly for a semiconductor device according to claim 21, wherein the output terminals of the casings have a first width, and wherein the first bus bar has a width several times greater than the first width.

23. The subassembly for a semiconductor device according to claim 22, wherein the first bus bar has a portion parallel to a side of the second bus bar, and the third bus bar has a portion parallel to an opposite side of the second bus bar.

27. The semiconductor device according to claim 21, wherein said bus bars have a wide surface area to decrease commutating inductance of a bridge connection, and are integrated with one another.

24. A semiconductor device of a high power capacity comprising:

a first casing having terminals extending from a top surface including

a signal input terminal,

a current output terminal, and

a current input terminal between the signal input terminal and the current output terminal;

a second casing, of substantially equivalent type of the first casing, having terminals extending from a top surface including

a signal input terminal,

a current input terminal, opposed to the current output terminal of the first casing, and

a current output terminal between the signal input terminal and the current input terminal;

power semiconductor devices of substantially equivalent electrical properties sealed respectively within said first and second casings; and

means for electrically connecting terminals of the first casing to terminals of the second casing so as to decrease commutating inductance.

25. A subassembly for a semiconductor device of a high power capacity comprising:

a first casing having a central first top portion at a first level;

a first pair of semiconductor chips sealed within the first casing;

a current input terminal and a current output terminal extending out of the first top portion;

a lower portion on a side of the first top portion at a level lower than the first level;

a first plurality of signal input terminals extending out of the lower portion;

another lower portion on an opposite side of the first top portion at the level lower than the first level;

a second plurality of signal input terminals extending out of the other lower portion, each signal input terminal of the second plurality connected within the first casing to a corresponding signal input terminal of the first plurality;

a second casing having a central second top portion at the first level;

a second pair of semiconductor chips sealed within the second casing;

a current input terminal and a current output terminal extending out of the second top portion;

a lower portion on a side of the second top portion at the level lower than the first level;

a third plurality of signal input terminals extending out of the lower portion on the side of the second top portion;

another lower portion on an opposite side of the second top portion at the level lower than the first level;

a fourth plurality of signal input terminals extending out of the other lower portion on the opposite side of the second top portion, each signal input terminal of the fourth plurality connected within the second casing to a corresponding signal input terminal of the third plurality; and

means for connecting terminals on the first top portion to terminals on the second top portion so as to decrease commutating inductance.