Method and apparatus for testing analogue circuits

• US 5,202,639 A
• Filed: 02/19/1992
• Issued: 04/13/1993
• Est. Priority Date: 01/09/1989
• Status: Expired due to Term

• Current Assignee: Diagnosys Limited Systems House
• Original Assignee: Schlumberger Technologies Ltd (SLB)
• Inventors: McKeon, Alice, Wakeling, Antony
• Primary Examiner(s): Harvey, Jack B.
• Application Number:
  US07/839,735
• Time in Patent Office: 419 Days
• Field of Search: 324/537, 324/522-524, 324/500, 324/158 R, 371/24, 371/25.1, 371/26
• US Class Current: 324/537
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/318392 for sequential circuits G01R31/318544 takes precedence
• CPC Class Codes: G06F 11/2273 Test methods

Abstract

An analogue circuit or unit under test is tested utilizing automatic test equipment and an interface unit to apply stimuli to the circuit the stimuli including supply potentials. A computer analyses the circuit as a network of nodes and modules to deduce a set of ranges of values at selected nodes, the ranges being determined from the set of the stimuli and a resultant set of test measurements, taken from nodes of the circuit by the interface and automatic test equipment, taking into account tolerances in the stimuli, the measurements and the nominal parameters of components of the circuit. If there is inconsistency among the derived ranges the computer treats as potentially faulty any module which could remove the inconsistency if the constraints imposed by that module were suspended. The computer controls an iterative, hierarchical process involving repetition of the sequence of steps using different sets of stimuli and/or measurements and/or different analyses of the circuit into nodes and modules, in particular with analysis in terms of successively smaller modules. In this way, the location of faults can be progressively narrowed down and corresponding output information can be given in a device such as a VDU or printer.

Claims

1. A method of testing an analogue circuit, the circuit comprising a network of electrical modules interconnected by nodes, each module comprising an electrical component or set of electrical components, the method comprising a measurement routine including the steps of

(1) interfacing the circuit to automatic test apparatus, said test apparatus comprising means for interfacing with said circuit, means for applying stimuli to said circuit and means for taking test measurements from said circuit,

(ii) selecting a set of stimuli, including supply potentials, for application to the circuit,

(iii) applying said set of stimuli to first nodes of said circuit via said interfacing means,

(iv) taking a set of test measurements from second nodes of the circuit via said interfacing means,

(v) conducting at least one analysis cycle, employing the automatic test apparatus for each analysis cycle, each analysis cycle comprising the steps of

(a) analyzing the circuit as a network of nodes connected by modules which impose constraints on signals passing between the nodes,

(b) using the set of stimuli, the test measurements, and the constraints, taking into account tolerances in all of said stimuli, measurements, and constraints, to derive at least two differently derived ranges of values of a signal variable propagated within the network at at least one of a complete set of nodes,

(c) detecting a fault if said differently derived ranges of the variable do not overlap so as to indicate an inconsistency, and

(d) if a fault is detected, repeating the analysis cycle which has led to a fault being detected with the constraints on a selected module removed, other than the constraint that all the currents into the module sum to zero, and treating said selected module as potentially faulty if such removal of constraints leads to a removal of the inconsistency.

2. A method according to claim 1, wherein, said measurement routine or an analysis cycle is conducted repeatedly in respect of a plurality of nodes.

3. A method according to claim 2, wherein in repeated routines or cycles further constraints are introduced by requiring a node at which derived ranges overlap to have a value of the variable lying within a new range which is the intersection of the overlapping ranges.

4. A method according to claim 3, wherein said further constraints are propagated in ensuing routines or analysis cycles into the derivation of ranges at other nodes.

5. A method according to claim 3, wherein an analysis cycle which has led to an inconsistency is repeated with the constraints on a selected module removed, other than the constraint that all the currents into the module sum to zero, and said selected module is treated as potentially faulty if such removal of constraints leads to removal of the inconsistency.

6. A method according to claim 1, wherein, when a fault has been detected, measurement routines using different stimuli are carried out to obtain additional information indicative of fault location.

7. A method according to claim 6, wherein said measurement routines are carried out in a hierarchical manner.

8. A method according to claim 7, wherein measurement routines are effected in terms of progressively smaller modules.

9. A method according to claim 1, and further including, when a fault has been detected, the step of carrying out measurement routines using different measurements to obtain additional information indicative of fault location.

10. A method according to claim 9, wherein said measurement routines are carried out in a heirarchical manner.

11. A method according to claim 10, wherein analysis is effected in terms of progressively smaller modules.

12. A method according to claim 1, and further including, when a fault has been detected, the step of carrying out analysis cycles using different analyses to obtain additional information indicative of fault location.

13. A method according to claim 12, wherein said analysis cycles are carried out in a heirarchical manner.

14. A method according to claim 13, wherein analysis is effected in terms of successively smaller modules.

15. A method according to claim 1, wherein the test measurements are all voltage measurements.

16. A method according to claim 1, wherein the derived ranges of values include both voltage and current values.

17. Test apparatus for testing an analogue circuit, the circuit comprising a network of electrical modules interconnected by nodes, each module comprising an electrical component or set of electrical components, the apparatus comprising

interface means for interfacing said circuit to the test apparatus,

means for applying a set of stimuli, including supply potentials, to the circuit at first nodes thereof via said interface means,

means for taking a set of test measurements from second nodes of the circuit via said interface means, and

data processing means for analyzing the circuit as a network of nodes connected by said modules which impose constraints on signals passing between the nodes, and deriving from the set of stimuli, measurements, and constraints imposed by the modules, taking into account tolerances in all of these, at least two differently derived ranges of values of a variable at at least one of the complete set of nodes, the ranges of values of a signal variable being derived by propagation within the network,

wherein the data processing means is further operative to determine whether differently derived ranges overlap or not, such that a fault is detected if said ranges do not overlap to indicate an inconsistency, and

if a fault is detected, the data processing means is further operative to analyze the circuit with the constraints on a selected module removed, other than the constraint that all the currents into the module sum to zero, said data processing means being operative to treat said selected module as potentially faulty if such removal of constraints leads to removal of the inconsistency.