P-code generation
First Claim
1. Apparatus for generation of a code sequence P(t) as a function of time t for use in determining position on a surface of a body such as the Earth from position data provided from one or more satellites, the apparatus comprising:
- a clock pulse source that provides a sequence of clock pulses of predetermined period T;
first clock control means having a clock pulse input terminal and a clock pulse output terminal, for receiving the sequence of clock pulses at the input terminal and passing through and issuing this sequence of clock pulses at the output terminal, the first clock control means further having a first control input terminal for halting pass-through of clock pulse sequences when a halt signal is received at this first control input terminal, and having a second control input terminal for resuming pass-through of clock pulse sequences when a reset signal is received at the second control input terminal after receipt of a halt signal at the first control input terminal;
second clock control means having a clock pulse input terminal and a clock pulse output terminal, for receiving the sequence of clock pulses at the input terminal and passing through and issuing this sequence of clock pulses at the output terminal, the second clock control means further having a first control input terminal for halting pass-through of clock pulse sequences when a halt signal is received at this first control input terminal, having a second control input terminal for resuming pass-through and issuance of clock pulse sequences when a reset signal is received at the second control input terminal after receipt of a halt signal at the first control input terminal;
third clock control means having a clock pulse input terminal and a clock pulse output terminal, for receiving the sequence of clock pulses at the input terminal and passing through and issuing this sequence of clock pulses at the output terminal, the third clock control means further having a first control input terminal for halting pass-through of clock pulse sequences when a halt signal is received at this first control input terminal, and having a second control input terminal for resuming pass-through of clock pulse sequences when a reset signal is received at the second control input terminal after receipt of a halt signal at the first control input terminal;
first, second, third and fourth register means that receive a clock pulse sequence from the first clock control means, from the clock pulse source, from the second clock control means and from the third clock control means, respectively, and generate and issue a predetermined code sequence X1B(t), X1A(t), X2A(t) and X2B(t), respectively, for each clock pulse received at a sequence of times t=mT (m=1, 2, . . . );
first decoder means, connected to the first register means, for receiving the code sequence values X1B(t) (t=m1 T;
m1 =1, 2, . . . M1) issued by the first register means, for detecting occurrence of a predetermined code sequence value X1B0, and for producing and issuing a first halt signal that is received by the first control input terminal of, and halts the pass-through of clock pulses at, the first clock control means when the predetermined code sequence value X1B0 is received, where M1 is a predetermined positive integer;
second decoder means, connected to the second register means, for receiving the code sequence values X1A(t) (t=m2 T;
m2 =1, 2, . . . M2) issued by the second register means, for detecting occurrence of a predetermined code sequence value X1A0, and for producing and issuing a first reset signal that is received by the second control input terminal of, and resumes the pass-through and issuance of clock pulses at, the first clock control means when the predetermined code sequence value X1A0 is received, where M2 is a predetermined positive integer;
third decoder means, connected to the third register means, for receiving the code sequence values X2A(t) (t=m3 T;
m3 =1, 2, . . . M3) issued by the third register means, for detecting occurrence of a predetermined code sequence value X2A0, and for producing and issuing a first halt signal that is received by the first control input terminal of, and halts the pass-through of clock pulses at, the second clock control means when the predetermined code sequence value X2A0 is received, where M3 is a predetermined positive integer;
fourth decoder means, connected to the fourth register means, for receiving the code sequence values X2B(t) (t=m4 T;
m4 =1, 2, . . . M4) issued by the fourth register means, for detecting occurrence of a predetermined code sequence value X2A0, and for producing and issuing a first halt signal that is received by the first control input terminal of, and halts the pass-through of clock pulses at, the third clock control means when the predetermined code sequence value X2B0 is received, where M4 is a predetermined positive integer;
a period counter that receives and counts the number of first reset signals issued by the second decoder means, that issues a first period counter output signal when this count has reached a fifth predetermined integer M5-1, and that issues a second period counter output signal when this count has reached the integer M5precession means for receiving a sequence of clock pulses from the clock pulse source, for receiving output signals from the third decoder means and from the fourth decoder means, and for receiving the first and second period counter output signals, for counting a predetermined number M6 of clock pulses, after receipt of a predetermined output signal from the third decoder means, and after receipt of a predetermined output signal from the first period counter, and for then issuing a second reset signal that is received by and commands the second clock control means and the third clock control means to resume pass-through and issuance of the sequence of clock pulses;
first logic means for receiving the first and second code sequences X1B(t) and X1A(t) and for forming and issuing an Exclusive-Or combination signal X1(t)=X1B(t) ⊕
X1A(t) as an output signal;
second logic means for receiving the third and fourth code sequences X2A(t) and X2B(t) and for forming and issuing a time delayed Exclusive-Or combination signal X2(t)=X2A(t-KT) ⊕
X2B(t-KT) as an output signal, where K is a predetermined non-negative integer;
third logic means for receiving the code sequence signal X1(t) and X2(t) and for forming and issuing an Exclusive-Or combination signal P(t)=X1(t) ⊕
X2(t);
where the third register means and the fourth register means include a first latch with a first latch choice input terminal and a second latch with a second latch choice input terminal, respectively, that allows a choice of the contents of the first and second register means, respectively, from among M6 different initial code sequence values for the third register means and from among M7 different code sequence values for the fourth register means, where M6 and M7 are predetermined positive integers.
5 Assignments
0 Petitions
Accused Products
Abstract
Improved apparatus for generation of the P-code sequences used in global positioning by issuance and sensing of code sequences issued by a plurality of satellites. The improved apparatus generates the same P-code sequences with fewer components, or with different components, by removal or replacement of: (1) a time delay/multiplexer module that allows choice of the satellite whose P-code is being formed and issued; (2) four 12-bit counters that determine the end of an epoch and are associated with four X code registers; (3) components that produce precession of an X1 code sequence relative to an X2 code sequence; and (4) an end-of-the-period counter, used to sense occurrence of the end of a chosen period, for example, 7.0 days, for purpose of P-code re-initialization.
-
Citations
24 Claims
-
1. Apparatus for generation of a code sequence P(t) as a function of time t for use in determining position on a surface of a body such as the Earth from position data provided from one or more satellites, the apparatus comprising:
-
a clock pulse source that provides a sequence of clock pulses of predetermined period T; first clock control means having a clock pulse input terminal and a clock pulse output terminal, for receiving the sequence of clock pulses at the input terminal and passing through and issuing this sequence of clock pulses at the output terminal, the first clock control means further having a first control input terminal for halting pass-through of clock pulse sequences when a halt signal is received at this first control input terminal, and having a second control input terminal for resuming pass-through of clock pulse sequences when a reset signal is received at the second control input terminal after receipt of a halt signal at the first control input terminal; second clock control means having a clock pulse input terminal and a clock pulse output terminal, for receiving the sequence of clock pulses at the input terminal and passing through and issuing this sequence of clock pulses at the output terminal, the second clock control means further having a first control input terminal for halting pass-through of clock pulse sequences when a halt signal is received at this first control input terminal, having a second control input terminal for resuming pass-through and issuance of clock pulse sequences when a reset signal is received at the second control input terminal after receipt of a halt signal at the first control input terminal; third clock control means having a clock pulse input terminal and a clock pulse output terminal, for receiving the sequence of clock pulses at the input terminal and passing through and issuing this sequence of clock pulses at the output terminal, the third clock control means further having a first control input terminal for halting pass-through of clock pulse sequences when a halt signal is received at this first control input terminal, and having a second control input terminal for resuming pass-through of clock pulse sequences when a reset signal is received at the second control input terminal after receipt of a halt signal at the first control input terminal; first, second, third and fourth register means that receive a clock pulse sequence from the first clock control means, from the clock pulse source, from the second clock control means and from the third clock control means, respectively, and generate and issue a predetermined code sequence X1B(t), X1A(t), X2A(t) and X2B(t), respectively, for each clock pulse received at a sequence of times t=mT (m=1, 2, . . . ); first decoder means, connected to the first register means, for receiving the code sequence values X1B(t) (t=m1 T;
m1 =1, 2, . . . M1) issued by the first register means, for detecting occurrence of a predetermined code sequence value X1B0, and for producing and issuing a first halt signal that is received by the first control input terminal of, and halts the pass-through of clock pulses at, the first clock control means when the predetermined code sequence value X1B0 is received, where M1 is a predetermined positive integer;second decoder means, connected to the second register means, for receiving the code sequence values X1A(t) (t=m2 T;
m2 =1, 2, . . . M2) issued by the second register means, for detecting occurrence of a predetermined code sequence value X1A0, and for producing and issuing a first reset signal that is received by the second control input terminal of, and resumes the pass-through and issuance of clock pulses at, the first clock control means when the predetermined code sequence value X1A0 is received, where M2 is a predetermined positive integer;third decoder means, connected to the third register means, for receiving the code sequence values X2A(t) (t=m3 T;
m3 =1, 2, . . . M3) issued by the third register means, for detecting occurrence of a predetermined code sequence value X2A0, and for producing and issuing a first halt signal that is received by the first control input terminal of, and halts the pass-through of clock pulses at, the second clock control means when the predetermined code sequence value X2A0 is received, where M3 is a predetermined positive integer;fourth decoder means, connected to the fourth register means, for receiving the code sequence values X2B(t) (t=m4 T;
m4 =1, 2, . . . M4) issued by the fourth register means, for detecting occurrence of a predetermined code sequence value X2A0, and for producing and issuing a first halt signal that is received by the first control input terminal of, and halts the pass-through of clock pulses at, the third clock control means when the predetermined code sequence value X2B0 is received, where M4 is a predetermined positive integer;a period counter that receives and counts the number of first reset signals issued by the second decoder means, that issues a first period counter output signal when this count has reached a fifth predetermined integer M5-1, and that issues a second period counter output signal when this count has reached the integer M5 precession means for receiving a sequence of clock pulses from the clock pulse source, for receiving output signals from the third decoder means and from the fourth decoder means, and for receiving the first and second period counter output signals, for counting a predetermined number M6 of clock pulses, after receipt of a predetermined output signal from the third decoder means, and after receipt of a predetermined output signal from the first period counter, and for then issuing a second reset signal that is received by and commands the second clock control means and the third clock control means to resume pass-through and issuance of the sequence of clock pulses; first logic means for receiving the first and second code sequences X1B(t) and X1A(t) and for forming and issuing an Exclusive-Or combination signal X1(t)=X1B(t) ⊕
X1A(t) as an output signal;second logic means for receiving the third and fourth code sequences X2A(t) and X2B(t) and for forming and issuing a time delayed Exclusive-Or combination signal X2(t)=X2A(t-KT) ⊕
X2B(t-KT) as an output signal, where K is a predetermined non-negative integer;third logic means for receiving the code sequence signal X1(t) and X2(t) and for forming and issuing an Exclusive-Or combination signal P(t)=X1(t) ⊕
X2(t);where the third register means and the fourth register means include a first latch with a first latch choice input terminal and a second latch with a second latch choice input terminal, respectively, that allows a choice of the contents of the first and second register means, respectively, from among M6 different initial code sequence values for the third register means and from among M7 different code sequence values for the fourth register means, where M6 and M7 are predetermined positive integers. - View Dependent Claims (2, 3, 4, 5)
-
-
6. Apparatus for generation of a code sequence P(t) as a function of time t for use in determining position on a surface of a body such as the Earth from position data provided from one or more satellites, the apparatus comprising:
-
a clock pulse source that provides a sequence of clock pulses of predetermined period T; first clock control means having a clock pulse input terminal and a clock pulse output terminal, for receiving the sequence of clock pulses at the input terminal and passing through and issuing this sequence of clock pulses at the output terminal, the first clock control means further having a first control input terminal for halting pass-through of clock pulse sequences when a halt signal is received at this first control input terminal, and having a second control input terminal for resuming pass-through of clock pulse sequences when a reset signal is received at the second control input terminal after receipt of a halt signal at the first control input terminal; second clock control means having a clock pulse input terminal and a clock pulse output terminal, for receiving the sequence of clock pulses at the input terminal and passing through and issuing this sequence of clock pulses at the output terminal, the second clock control means further having a first control input terminal for halting pass-through of clock pulse sequences when a halt signal is received at this first control input terminal, having a second control input terminal for resuming pass-through and issuance of clock pulse sequences when a reset signal is received at the second control input terminal after receipt of a halt signal at the first control input terminal, and having a control output terminal for issuing a predetermined halt flag signal HF(t) when a halt flag signal has been received at the first control input terminal and a reset signal has not yet been subsequently received at the second control input terminal; first, second, third and fourth register means that receive a clock pulse sequence from the first clock control means, from the clock pulse source, from the second clock control means and from the third clock control means, respectively, and generate and issue a predetermined code sequence X1B(t), X1A(t), X2A(t) and X2B(t), respectively, for each clock pulse received at a sequence of times t=mT (m=1, 2, . . . ); first decoder means, having a plurality of input terminals and a plurality of output terminals and being connected to the first register means and to the second register means, for receiving the code sequence values X1B(t) (t=m1 T;
m1 =1, 2, . . . M1) issued by the first register means, for receiving the code sequence values X1A(t) (t=m2 T;
m2 =1, 2, . . . M2) issued by the second register means, for detecting receipt of a predetermined code sequence value X1B0 from the first register means, for detecting receipt of a predetermined code sequence value X1A0 from the second register means, for producing and issuing a first halt signal that is received by the first control input terminal of, and halts the pass-through of clock pulses at, the first clock control means when the predetermined code sequence value X1B0 is received, and for producing and issuing a first reset signal that is received by the second clock control input terminal of, and resumes the pass-through and issuance of clock pulses at, the first clock control means when the predetermined code sequence X1A0 is received, where M1 and M2 are predetermined positive integers;second decoder means, having a plurality of input terminals and a plurality of output terminals and being connected to the third register means and to the fourth register means, for receiving the code sequence values X2A(t) (t=m3 T;
m3 =1, 2, . . . , M3) issued by the third register means, for detecting receipt of a predetermined code sequence value X2A0 or of a predetermined code sequence value X2A1 from the third register means, for receiving the code sequence values X2B(t) (t=m4 T;
m4 =1, 2, . . . , M4) issued by the fourth register means, for detecting receipt of a predetermined code sequence value X2B0 or of a predetermined code sequence value X2B1 from the fourth register means, for predetermined positive integers M3 and M4 with M3>
M4, for receiving the halt flag signal HF(t), for issuing at a first output terminal a second halt signal that is received by the first control input terminal of, and halts the pass-through of clock pulses at, the second clock control means when the predetermined code sequence value X2B0 or X2B1 is received from the fourth register means, for issuing at a second output terminal a second reset signal that is received by the second control input terminal of, and resumes the pass-through and issuance of clock pulses at, the second clock control means when the predetermined code sequence value X2A0 or X2A1 is received from the third register means, and for issuing at a third output terminal a set/clear control signal SC(t), which has a first predetermined value when m3 =M3-k (k=1, 2, . . . , M5;
M5 a predetermined positive integer) at a time preceding receipt of each of said second reset signals by said second clock control means, and which has a second predetermined value otherwise;gated logic means, having four input terminals and an output terminal, for receiving the code sequences X2A(t) and X2B(t) at the first and second input terminals, for receiving the halt flag signal HF(t) at a third input terminal, for receiving the set/clear signal SC(t) at the fourth input terminal, and for producing and issuing at its output terminal an output signal X2(t) that is equal to X2A(t) ⊕
X2B(t) when HF(t)=0 and SC(t)=0, that is equal to X2A(t) when HF(t)=1 and SC(t)=0, that is equal to X2B(t)* when HF(t)=0 and SC(t)=1, and that is equal to 1 when HF(t)=1 and SC(t)=1;first logic means, having two input terminals and an output terminal, for receiving the first and second code sequences X1B(t) and X1A(t) at its input terminals and for forming and issuing an Exclusive-Or combination X1(t)=X1B(t) ⊕
X1A(t) at its output terminal;time delay means, having two input terminals and an output terminal, for receiving the signal X2(t) at its first input terminal and for receiving a positive integer M6 at its second input terminal, and for forming and issuing a time delayed output signal X2(t-(M6)T) at its output terminal; second logic means, having two input terminals and an output terminal, for receiving the signals X1(t) and X2(t-(M6)T) at its input terminals and for forming and issuing a signal P(t)=X1(t) ⊕
X2(t-(M6)T) at its output terminal; andsequence choice means, connected to the second input terminal of the time delay means, for selecting the integer M6. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
-
Specification